drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h

Extension

.h

Size

3742 bytes

Lines

152

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_
#define ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_

/*
 *****************************************
 *   DCORE0_TPC0_EML_SPMU
 *   (Prototype: SPMU)
 *****************************************
 */

#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 0x1000

#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 0x1008

#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 0x1010

#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 0x1018

#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 0x1020

#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 0x1028

#define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 0x10F8

#define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 0x10FC

#define mmDCORE0_TPC0_EML_SPMU_PMTRC 0x1200

#define mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST 0x1204

#define mmDCORE0_TPC0_EML_SPMU_TRC_STAT_HOST 0x1208

#define mmDCORE0_TPC0_EML_SPMU_TRC_EN_HOST 0x120C

#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER0_EL0 0x1400

#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER1_EL0 0x1404

#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER2_EL0 0x1408

#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER3_EL0 0x140C

#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER4_EL0 0x1410

#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER5_EL0 0x1414

#define mmDCORE0_TPC0_EML_SPMU_PMSSR 0x1610

#define mmDCORE0_TPC0_EML_SPMU_PMOVSSR 0x1614

#define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_L 0x1618

#define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_H 0x161C

#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR0 0x1620

#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR1 0x1624

#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR2 0x1628

#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR3 0x162C

#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR4 0x1630

#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR5 0x1634

#define mmDCORE0_TPC0_EML_SPMU_PMSCR 0x16F0

#define mmDCORE0_TPC0_EML_SPMU_PMSRR 0x16F4

#define mmDCORE0_TPC0_EML_SPMU_PMCNTENSET_EL0 0x1C00

#define mmDCORE0_TPC0_EML_SPMU_PMCNTENCLR_EL0 0x1C20

#define mmDCORE0_TPC0_EML_SPMU_PMINTENSET_EL1 0x1C40

#define mmDCORE0_TPC0_EML_SPMU_PMINTENCLR_EL1 0x1C60

#define mmDCORE0_TPC0_EML_SPMU_PMOVSCLR_EL0 0x1C80

#define mmDCORE0_TPC0_EML_SPMU_PMSWINC_EL0 0x1CA0

#define mmDCORE0_TPC0_EML_SPMU_PMOVSSET_EL0 0x1CC0

#define mmDCORE0_TPC0_EML_SPMU_PMCFGR 0x1E00

#define mmDCORE0_TPC0_EML_SPMU_PMCR_EL0 0x1E04

#define mmDCORE0_TPC0_EML_SPMU_PMITCTRL 0x1F00

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.