drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_stm_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_stm_regs.h

Extension

.h

Size

3160 bytes

Lines

132

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_
#define ASIC_REG_DCORE0_TPC0_EML_STM_REGS_H_

/*
 *****************************************
 *   DCORE0_TPC0_EML_STM
 *   (Prototype: STM)
 *****************************************
 */

#define mmDCORE0_TPC0_EML_STM_STMDMASTARTR 0x3C04

#define mmDCORE0_TPC0_EML_STM_STMDMASTOPR 0x3C08

#define mmDCORE0_TPC0_EML_STM_STMDMASTATR 0x3C0C

#define mmDCORE0_TPC0_EML_STM_STMDMACTLR 0x3C10

#define mmDCORE0_TPC0_EML_STM_STMDMAIDR 0x3CFC

#define mmDCORE0_TPC0_EML_STM_STMHEER 0x3D00

#define mmDCORE0_TPC0_EML_STM_STMHETER 0x3D20

#define mmDCORE0_TPC0_EML_STM_STMHEBSR 0x3D60

#define mmDCORE0_TPC0_EML_STM_STMHEMCR 0x3D64

#define mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR 0x3D68

#define mmDCORE0_TPC0_EML_STM_STMHEMASTR 0x3DF4

#define mmDCORE0_TPC0_EML_STM_STMHEFEAT1R 0x3DF8

#define mmDCORE0_TPC0_EML_STM_STMHEIDR 0x3DFC

#define mmDCORE0_TPC0_EML_STM_STMSPER 0x3E00

#define mmDCORE0_TPC0_EML_STM_STMSPTER 0x3E20

#define mmDCORE0_TPC0_EML_STM_STMSPSCR 0x3E60

#define mmDCORE0_TPC0_EML_STM_STMSPMSCR 0x3E64

#define mmDCORE0_TPC0_EML_STM_STMSPOVERRIDER 0x3E68

#define mmDCORE0_TPC0_EML_STM_STMSPMOVERRIDER 0x3E6C

#define mmDCORE0_TPC0_EML_STM_STMSPTRIGCSR 0x3E70

#define mmDCORE0_TPC0_EML_STM_STMTCSR 0x3E80

#define mmDCORE0_TPC0_EML_STM_STMTSSTIMR 0x3E84

#define mmDCORE0_TPC0_EML_STM_STMTSFREQR 0x3E8C

#define mmDCORE0_TPC0_EML_STM_STMSYNCR 0x3E90

#define mmDCORE0_TPC0_EML_STM_STMAUXCR 0x3E94

#define mmDCORE0_TPC0_EML_STM_STMFEAT1R 0x3EA0

#define mmDCORE0_TPC0_EML_STM_STMFEAT2R 0x3EA4

#define mmDCORE0_TPC0_EML_STM_STMFEAT3R 0x3EA8

#define mmDCORE0_TPC0_EML_STM_STMITTRIGGER 0x3EE8

#define mmDCORE0_TPC0_EML_STM_STMITATBDATA0 0x3EEC

#define mmDCORE0_TPC0_EML_STM_STMITATBCTR2 0x3EF0

#define mmDCORE0_TPC0_EML_STM_STMITATBID 0x3EF4

#define mmDCORE0_TPC0_EML_STM_STMITATBCTR0 0x3EF8

#define mmDCORE0_TPC0_EML_STM_STMITCTRL 0x3F00

#define mmDCORE0_TPC0_EML_STM_STMCLAIMSET 0x3FA0

#define mmDCORE0_TPC0_EML_STM_STMCLAIMCLR 0x3FA4

#define mmDCORE0_TPC0_EML_STM_STMLAR 0x3FB0

#define mmDCORE0_TPC0_EML_STM_STMLSR 0x3FB4

#define mmDCORE0_TPC0_EML_STM_STMAUTHSTATUS 0x3FB8

#define mmDCORE0_TPC0_EML_STM_STMDEVARCH 0x3FBC

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.