drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_arc_aux_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_arc_aux_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_qm_arc_aux_regs.h
Extension
.h
Size
18455 bytes
Lines
592
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_
#define ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_

/*
 *****************************************
 *   DCORE0_TPC0_QM_ARC_AUX
 *   (Prototype: QMAN_ARC_AUX)
 *****************************************
 */

#define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ 0x4008100

#define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK 0x4008104

#define mmDCORE0_TPC0_QM_ARC_AUX_RST_VEC_ADDR 0x4008108

#define mmDCORE0_TPC0_QM_ARC_AUX_DBG_MODE 0x400810C

#define mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM 0x4008110

#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_NUM 0x4008114

#define mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT 0x4008118

#define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x400811C

#define mmDCORE0_TPC0_QM_ARC_AUX_CTI_AP_STS 0x4008120

#define mmDCORE0_TPC0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4008124

#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST 0x4008128

#define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ 0x400812C

#define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4008130

#define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4008134

#define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4008138

#define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_MSB_ADDR 0x400813C

#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LSB_ADDR 0x4008140

#define mmDCORE0_TPC0_QM_ARC_AUX_CFG_MSB_ADDR 0x4008144

#define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4008150

#define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4008154

#define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4008158

#define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_MSB_ADDR 0x400815C

#define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4008160

#define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4008164

#define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4008168

#define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_MSB_ADDR 0x400816C

#define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_OFFSET 0x4008170

#define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_OFFSET 0x4008174

#define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_OFFSET 0x4008178

#define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_OFFSET 0x400817C

#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4008180

#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4008184

#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4008188

#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x400818C

#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4008190

#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4008194

#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4008198

#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x400819C

#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x40081A0

#define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x40081A4

Annotation

Implementation Notes