drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_regs.h
Extension
.h
Size
7529 bytes
Lines
246
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_
#define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_

/*
 *****************************************
 *   DCORE0_VDEC0_BRDG_CTRL
 *   (Prototype: VDEC_BRDG_CTRL)
 *****************************************
 */

#define mmDCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE 0x41E3100

#define mmDCORE0_VDEC0_BRDG_CTRL_IDLE_MASK 0x41E3104

#define mmDCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT 0x41E3108

#define mmDCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT 0x41E310C

#define mmDCORE0_VDEC0_BRDG_CTRL_GRACEFUL 0x41E3110

#define mmDCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT 0x41E3114

#define mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR 0x41E3120

#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE 0x41E3124

#define mmDCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE 0x41E3128

#define mmDCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM 0x41E312C

#define mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK 0x41E3130

#define mmDCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK 0x41E3134

#define mmDCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK 0x41E3138

#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK 0x41E3160

#define mmDCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK 0x41E3170

#define mmDCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK 0x41E3180

#define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK 0x41E3190

#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT 0x41E31A0

#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT 0x41E31A4

#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT 0x41E31B0

#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT 0x41E31B4

#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT 0x41E31C0

#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT 0x41E31C4

#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE 0x41E31D0

#define mmDCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK 0x41E3200

#define mmDCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA 0x41E3230

#define mmDCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA 0x41E3260

#define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL 0x41E3270

#define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR 0x41E3280

#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L 0x41E3290

#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H 0x41E3294

#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L 0x41E32A0

#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H 0x41E32A4

#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L 0x41E32B0

#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H 0x41E32B4

#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L 0x41E32C0

#define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H 0x41E32C4

#define mmDCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN 0x41E32D0

#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK 0x41E3300

#define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK 0x41E3310

Annotation

Implementation Notes