drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore1_mme_ctrl_lo_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore1_mme_ctrl_lo_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore1_mme_ctrl_lo_regs.h
Extension
.h
Size
4447 bytes
Lines
164
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_DCORE1_MME_CTRL_LO_REGS_H_
#define ASIC_REG_DCORE1_MME_CTRL_LO_REGS_H_

/*
 *****************************************
 *   DCORE1_MME_CTRL_LO
 *   (Prototype: MME_CTRL_LO)
 *****************************************
 */

#define mmDCORE1_MME_CTRL_LO_ARCH_STATUS 0x42CB000

#define mmDCORE1_MME_CTRL_LO_CMD 0x42CB004

#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 0x42CB148

#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 0x42CB14C

#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 0x42CB150

#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 0x42CB154

#define mmDCORE1_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 0x42CB158

#define mmDCORE1_MME_CTRL_LO_ARCH_A_SS 0x42CB224

#define mmDCORE1_MME_CTRL_LO_ARCH_B_SS 0x42CB228

#define mmDCORE1_MME_CTRL_LO_ARCH_COUT_SS 0x42CB27C

#define mmDCORE1_MME_CTRL_LO_QM_STALL 0x42CB400

#define mmDCORE1_MME_CTRL_LO_LOG_SHADOW_LO 0x42CB404

#define mmDCORE1_MME_CTRL_LO_LOG_SHADOW_HI 0x42CB408

#define mmDCORE1_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH 0x42CB40C

#define mmDCORE1_MME_CTRL_LO_REDUN 0x42CB410

#define mmDCORE1_MME_CTRL_LO_EUS_LOCAL_FIFO_TH 0x42CB414

#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 0x42CB418

#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 0x42CB41C

#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 0x42CB420

#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 0x42CB424

#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 0x42CB428

#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I 0x42CB42C

#define mmDCORE1_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 0x42CB430

#define mmDCORE1_MME_CTRL_LO_PCU_RL_DESC0 0x42CB434

#define mmDCORE1_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE 0x42CB438

#define mmDCORE1_MME_CTRL_LO_PCU_RL_TH 0x42CB43C

#define mmDCORE1_MME_CTRL_LO_PCU_RL_MIN 0x42CB440

#define mmDCORE1_MME_CTRL_LO_PCU_RL_CTRL_EN 0x42CB444

#define mmDCORE1_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE 0x42CB448

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_BF16 0x42CB44C

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_BF16 0x42CB450

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_FP16 0x42CB454

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_FP16 0x42CB458

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_F8 0x42CB45C

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD 0x42CB460

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN 0x42CB464

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD 0x42CB468

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN 0x42CB46C

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD 0x42CB470

#define mmDCORE1_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN 0x42CB474

Annotation

Implementation Notes