drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h

File Facts

System: Linux kernel
Corpus path: drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_blocks_linux_driver.h
Extension: .h
Size: 2456864 bytes
Lines: 45068
Domain: Driver Families
Bucket: drivers/accel
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef GAUDI2_BLOCKS_LINUX_DRIVER_H_
#define GAUDI2_BLOCKS_LINUX_DRIVER_H_

#define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
#define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
#define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
#define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
#define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
#define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
#define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_ETF_SECTION 0x1000
#define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
#define DCORE0_TPC0_EML_STM_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_STM_SECTION 0x2000
#define mmDCORE0_TPC0_EML_CTI_BASE 0x5000ull
#define DCORE0_TPC0_EML_CTI_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_CTI_SECTION 0x1000
#define mmDCORE0_TPC0_EML_FUNNEL_BASE 0x6000ull
#define DCORE0_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_FUNNEL_SECTION 0x1000
#define mmDCORE0_TPC0_EML_BUSMON_0_BASE 0x7000ull
#define DCORE0_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_BUSMON_0_SECTION 0x1000
#define mmDCORE0_TPC0_EML_BUSMON_1_BASE 0x8000ull
#define DCORE0_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_BUSMON_1_SECTION 0x1000
#define mmDCORE0_TPC0_EML_BUSMON_2_BASE 0x9000ull
#define DCORE0_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_BUSMON_2_SECTION 0x1000
#define mmDCORE0_TPC0_EML_BUSMON_3_BASE 0xA000ull
#define DCORE0_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_BUSMON_3_SECTION 0x1000
#define mmDCORE0_TPC0_QM_ARC_RTT_BASE 0xB000ull
#define DCORE0_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400
#define DCORE0_TPC0_QM_ARC_RTT_SECTION 0x35000
#define mmDCORE0_TPC0_EML_CFG_BASE 0x40000ull
#define DCORE0_TPC0_EML_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_CFG_SECTION 0xE800
#define mmDCORE0_TPC0_EML_CFG_SPECIAL_BASE 0x40E80ull
#define DCORE0_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800
#define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x41000ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800
#define mmDCORE0_TPC0_EML_TPC_CFG_BASE 0x41000ull
#define DCORE0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000
#define DCORE0_TPC0_EML_TPC_CFG_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x41050ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x410A0ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x410F0ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x41140ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x41190ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x411E0ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x41230ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x41280ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x412D0ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x41320ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x41370ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x413C0ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x41410ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000
#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x41460ull
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000
#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000

Annotation

Atlas domain: Driver Families / drivers/accel.
Implementation status: source implementation candidate.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.