drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

File Facts

System: Linux kernel
Corpus path: drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h
Extension: .h
Size: 26210 bytes
Lines: 573
Domain: Driver Families
Bucket: drivers/accel
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

gaudi2_blocks_linux_driver.h
psoc_reset_conf_regs.h
psoc_global_conf_regs.h
cpu_if_regs.h
pcie_aux_regs.h
pcie_dbi_regs.h
pcie_wrap_regs.h
pmmu_hbw_stlb_regs.h
psoc_timestamp_regs.h
psoc_etr_regs.h
xbar_edge_0_regs.h
xbar_mid_0_regs.h
arc_farm_kdma_regs.h
arc_farm_kdma_ctx_regs.h
arc_farm_kdma_kdma_cgm_regs.h
arc_farm_arc0_aux_regs.h
arc_farm_arc0_acp_eng_regs.h
arc_farm_kdma_ctx_axuser_regs.h
arc_farm_arc0_dup_eng_axuser_regs.h
arc_farm_arc0_dup_eng_regs.h
dcore0_sync_mngr_objs_regs.h
dcore0_sync_mngr_glbl_regs.h
dcore0_sync_mngr_mstr_if_axuser_regs.h
dcore1_sync_mngr_glbl_regs.h
pdma0_qm_arc_aux_regs.h
pdma0_core_ctx_regs.h
pdma0_core_regs.h
pdma0_qm_axuser_secured_regs.h
pdma0_qm_regs.h
pdma0_qm_cgm_regs.h
pdma0_core_ctx_axuser_regs.h
pdma1_core_ctx_axuser_regs.h

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_GAUDI2_REGS_H_
#define ASIC_REG_GAUDI2_REGS_H_

#include "gaudi2_blocks_linux_driver.h"
#include "psoc_reset_conf_regs.h"
#include "psoc_global_conf_regs.h"
#include "cpu_if_regs.h"
#include "pcie_aux_regs.h"
#include "pcie_dbi_regs.h"
#include "pcie_wrap_regs.h"
#include "pmmu_hbw_stlb_regs.h"
#include "psoc_timestamp_regs.h"
#include "psoc_etr_regs.h"
#include "xbar_edge_0_regs.h"
#include "xbar_mid_0_regs.h"
#include "arc_farm_kdma_regs.h"
#include "arc_farm_kdma_ctx_regs.h"
#include "arc_farm_kdma_kdma_cgm_regs.h"
#include "arc_farm_arc0_aux_regs.h"
#include "arc_farm_arc0_acp_eng_regs.h"
#include "arc_farm_kdma_ctx_axuser_regs.h"
#include "arc_farm_arc0_dup_eng_axuser_regs.h"
#include "arc_farm_arc0_dup_eng_regs.h"
#include "dcore0_sync_mngr_objs_regs.h"
#include "dcore0_sync_mngr_glbl_regs.h"
#include "dcore0_sync_mngr_mstr_if_axuser_regs.h"
#include "dcore1_sync_mngr_glbl_regs.h"
#include "pdma0_qm_arc_aux_regs.h"
#include "pdma0_core_ctx_regs.h"
#include "pdma0_core_regs.h"
#include "pdma0_qm_axuser_secured_regs.h"
#include "pdma0_qm_regs.h"
#include "pdma0_qm_cgm_regs.h"
#include "pdma0_core_ctx_axuser_regs.h"
#include "pdma1_core_ctx_axuser_regs.h"
#include "pdma0_qm_axuser_nonsecured_regs.h"
#include "pdma1_qm_axuser_nonsecured_regs.h"
#include "dcore0_tpc0_qm_regs.h"
#include "dcore0_tpc0_qm_cgm_regs.h"
#include "dcore0_tpc0_qm_axuser_nonsecured_regs.h"
#include "dcore0_tpc0_qm_arc_aux_regs.h"
#include "dcore0_tpc0_cfg_regs.h"
#include "dcore0_tpc0_cfg_qm_regs.h"
#include "dcore0_tpc0_cfg_axuser_regs.h"
#include "dcore0_tpc0_cfg_qm_sync_object_regs.h"
#include "dcore0_tpc0_cfg_kernel_regs.h"
#include "dcore0_tpc0_cfg_kernel_tensor_0_regs.h"
#include "dcore0_tpc0_cfg_qm_tensor_0_regs.h"
#include "dcore0_tpc0_cfg_special_regs.h"
#include "dcore0_tpc0_eml_funnel_regs.h"
#include "dcore0_tpc0_eml_etf_regs.h"
#include "dcore0_tpc0_eml_stm_regs.h"
#include "dcore0_tpc0_eml_busmon_0_regs.h"
#include "dcore0_tpc0_eml_spmu_regs.h"
#include "pmmu_pif_regs.h"
#include "dcore0_edma0_qm_cgm_regs.h"
#include "dcore0_edma0_core_regs.h"
#include "dcore0_edma0_qm_regs.h"
#include "dcore0_edma0_qm_arc_aux_regs.h"
#include "dcore0_edma0_core_ctx_regs.h"
#include "dcore0_edma0_core_ctx_axuser_regs.h"
#include "dcore0_edma0_qm_axuser_nonsecured_regs.h"
#include "dcore0_edma1_core_ctx_axuser_regs.h"
#include "dcore0_edma1_qm_axuser_nonsecured_regs.h"
#include "dcore0_hmmu0_stlb_regs.h"
#include "dcore0_hmmu0_mmu_regs.h"
#include "rot0_qm_regs.h"
#include "rot0_qm_cgm_regs.h"
#include "rot0_qm_arc_aux_regs.h"
#include "rot0_regs.h"
#include "rot0_desc_regs.h"
#include "rot0_qm_axuser_nonsecured_regs.h"
#include "dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h"
#include "dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h"
#include "dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h"
#include "dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h"
#include "dcore0_rtr0_ctrl_regs.h"
#include "dcore0_dec0_cmd_regs.h"
#include "dcore0_vdec0_brdg_ctrl_regs.h"
#include "dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h"
#include "dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h"
#include "dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h"
#include "dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h"
#include "dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h"
#include "dcore0_vdec0_ctrl_special_regs.h"
#include "pcie_vdec0_brdg_ctrl_axuser_dec_regs.h"
#include "pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h"
#include "pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h"
#include "pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h"
#include "pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h"

Annotation

Immediate include surface: `gaudi2_blocks_linux_driver.h`, `psoc_reset_conf_regs.h`, `psoc_global_conf_regs.h`, `cpu_if_regs.h`, `pcie_aux_regs.h`, `pcie_dbi_regs.h`, `pcie_wrap_regs.h`, `pmmu_hbw_stlb_regs.h`.
Atlas domain: Driver Families / drivers/accel.
Implementation status: source implementation candidate.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.