drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm_arc_aux0_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm_arc_aux0_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm_arc_aux0_regs.h
Extension
.h
Size
16727 bytes
Lines
592
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_
#define ASIC_REG_NIC0_QM_ARC_AUX0_REGS_H_

/*
 *****************************************
 *   NIC0_QM_ARC_AUX0
 *   (Prototype: QMAN_ARC_AUX)
 *****************************************
 */

#define mmNIC0_QM_ARC_AUX0_RUN_HALT_REQ 0x5418100

#define mmNIC0_QM_ARC_AUX0_RUN_HALT_ACK 0x5418104

#define mmNIC0_QM_ARC_AUX0_RST_VEC_ADDR 0x5418108

#define mmNIC0_QM_ARC_AUX0_DBG_MODE 0x541810C

#define mmNIC0_QM_ARC_AUX0_CLUSTER_NUM 0x5418110

#define mmNIC0_QM_ARC_AUX0_ARC_NUM 0x5418114

#define mmNIC0_QM_ARC_AUX0_WAKE_UP_EVENT 0x5418118

#define mmNIC0_QM_ARC_AUX0_DCCM_SYS_ADDR_BASE 0x541811C

#define mmNIC0_QM_ARC_AUX0_CTI_AP_STS 0x5418120

#define mmNIC0_QM_ARC_AUX0_CTI_CFG_MUX_SEL 0x5418124

#define mmNIC0_QM_ARC_AUX0_ARC_RST 0x5418128

#define mmNIC0_QM_ARC_AUX0_ARC_RST_REQ 0x541812C

#define mmNIC0_QM_ARC_AUX0_SRAM_LSB_ADDR 0x5418130

#define mmNIC0_QM_ARC_AUX0_SRAM_MSB_ADDR 0x5418134

#define mmNIC0_QM_ARC_AUX0_PCIE_LSB_ADDR 0x5418138

#define mmNIC0_QM_ARC_AUX0_PCIE_MSB_ADDR 0x541813C

#define mmNIC0_QM_ARC_AUX0_CFG_LSB_ADDR 0x5418140

#define mmNIC0_QM_ARC_AUX0_CFG_MSB_ADDR 0x5418144

#define mmNIC0_QM_ARC_AUX0_HBM0_LSB_ADDR 0x5418150

#define mmNIC0_QM_ARC_AUX0_HBM0_MSB_ADDR 0x5418154

#define mmNIC0_QM_ARC_AUX0_HBM1_LSB_ADDR 0x5418158

#define mmNIC0_QM_ARC_AUX0_HBM1_MSB_ADDR 0x541815C

#define mmNIC0_QM_ARC_AUX0_HBM2_LSB_ADDR 0x5418160

#define mmNIC0_QM_ARC_AUX0_HBM2_MSB_ADDR 0x5418164

#define mmNIC0_QM_ARC_AUX0_HBM3_LSB_ADDR 0x5418168

#define mmNIC0_QM_ARC_AUX0_HBM3_MSB_ADDR 0x541816C

#define mmNIC0_QM_ARC_AUX0_HBM0_OFFSET 0x5418170

#define mmNIC0_QM_ARC_AUX0_HBM1_OFFSET 0x5418174

#define mmNIC0_QM_ARC_AUX0_HBM2_OFFSET 0x5418178

#define mmNIC0_QM_ARC_AUX0_HBM3_OFFSET 0x541817C

#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_0 0x5418180

#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_1 0x5418184

#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_2 0x5418188

#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_3 0x541818C

#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_4 0x5418190

#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_5 0x5418194

#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_LSB_ADDR_6 0x5418198

#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_0 0x541819C

#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_1 0x54181A0

#define mmNIC0_QM_ARC_AUX0_GENERAL_PURPOSE_MSB_ADDR_2 0x54181A4

Annotation

Implementation Notes