drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h
Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h- Extension
.h- Size
- 25285 bytes
- Lines
- 1058
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef ASIC_REG_NIC0_QM0_REGS_H_
#define ASIC_REG_NIC0_QM0_REGS_H_
/*
*****************************************
* NIC0_QM0
* (Prototype: QMAN)
*****************************************
*/
#define mmNIC0_QM0_GLBL_CFG0 0x541A000
#define mmNIC0_QM0_GLBL_CFG1 0x541A004
#define mmNIC0_QM0_GLBL_CFG2 0x541A008
#define mmNIC0_QM0_GLBL_ERR_CFG 0x541A00C
#define mmNIC0_QM0_GLBL_ERR_CFG1 0x541A010
#define mmNIC0_QM0_GLBL_ERR_ARC_HALT_EN 0x541A014
#define mmNIC0_QM0_GLBL_AXCACHE 0x541A018
#define mmNIC0_QM0_GLBL_STS0 0x541A01C
#define mmNIC0_QM0_GLBL_STS1 0x541A020
#define mmNIC0_QM0_GLBL_ERR_STS_0 0x541A024
#define mmNIC0_QM0_GLBL_ERR_STS_1 0x541A028
#define mmNIC0_QM0_GLBL_ERR_STS_2 0x541A02C
#define mmNIC0_QM0_GLBL_ERR_STS_3 0x541A030
#define mmNIC0_QM0_GLBL_ERR_STS_4 0x541A034
#define mmNIC0_QM0_GLBL_ERR_MSG_EN_0 0x541A038
#define mmNIC0_QM0_GLBL_ERR_MSG_EN_1 0x541A03C
#define mmNIC0_QM0_GLBL_ERR_MSG_EN_2 0x541A040
#define mmNIC0_QM0_GLBL_ERR_MSG_EN_3 0x541A044
#define mmNIC0_QM0_GLBL_ERR_MSG_EN_4 0x541A048
#define mmNIC0_QM0_GLBL_PROT 0x541A04C
#define mmNIC0_QM0_PQ_BASE_LO_0 0x541A050
#define mmNIC0_QM0_PQ_BASE_LO_1 0x541A054
#define mmNIC0_QM0_PQ_BASE_LO_2 0x541A058
#define mmNIC0_QM0_PQ_BASE_LO_3 0x541A05C
#define mmNIC0_QM0_PQ_BASE_HI_0 0x541A060
#define mmNIC0_QM0_PQ_BASE_HI_1 0x541A064
#define mmNIC0_QM0_PQ_BASE_HI_2 0x541A068
#define mmNIC0_QM0_PQ_BASE_HI_3 0x541A06C
#define mmNIC0_QM0_PQ_SIZE_0 0x541A070
#define mmNIC0_QM0_PQ_SIZE_1 0x541A074
#define mmNIC0_QM0_PQ_SIZE_2 0x541A078
#define mmNIC0_QM0_PQ_SIZE_3 0x541A07C
#define mmNIC0_QM0_PQ_PI_0 0x541A080
#define mmNIC0_QM0_PQ_PI_1 0x541A084
#define mmNIC0_QM0_PQ_PI_2 0x541A088
#define mmNIC0_QM0_PQ_PI_3 0x541A08C
#define mmNIC0_QM0_PQ_CI_0 0x541A090
#define mmNIC0_QM0_PQ_CI_1 0x541A094
#define mmNIC0_QM0_PQ_CI_2 0x541A098
#define mmNIC0_QM0_PQ_CI_3 0x541A09C
Annotation
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.