drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h
Extension
.h
Size
11032 bytes
Lines
422
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_PCIE_DBI_REGS_H_
#define ASIC_REG_PCIE_DBI_REGS_H_

/*
 *****************************************
 *   PCIE_DBI
 *   (Prototype: PCIE_DBI)
 *****************************************
 */

#define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0x4C02000

#define mmPCIE_DBI_STATUS_COMMAND_REG 0x4C02004

#define mmPCIE_DBI_CLASS_CODE_REVISION_ID 0x4C02008

#define mmPCIE_DBI_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG 0x4C0200C

#define mmPCIE_DBI_BAR0_REG 0x4C02010

#define mmPCIE_DBI_BAR1_REG 0x4C02014

#define mmPCIE_DBI_BAR2_REG 0x4C02018

#define mmPCIE_DBI_BAR3_REG 0x4C0201C

#define mmPCIE_DBI_BAR4_REG 0x4C02020

#define mmPCIE_DBI_BAR5_REG 0x4C02024

#define mmPCIE_DBI_CARDBUS_CIS_PTR_REG 0x4C02028

#define mmPCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG 0x4C0202C

#define mmPCIE_DBI_EXP_ROM_BASE_ADDR_REG 0x4C02030

#define mmPCIE_DBI_PCI_CAP_PTR_REG 0x4C02034

#define mmPCIE_DBI_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG 0x4C0203C

#define mmPCIE_DBI_CAP_ID_NXT_PTR_REG 0x4C02040

#define mmPCIE_DBI_CON_STATUS_REG 0x4C02044

#define mmPCIE_DBI_PCI_MSI_CAP_ID_NEXT_CTRL_REG 0x4C02050

#define mmPCIE_DBI_MSI_CAP_OFF_04H_REG 0x4C02054

#define mmPCIE_DBI_MSI_CAP_OFF_08H_REG 0x4C02058

#define mmPCIE_DBI_MSI_CAP_OFF_0CH_REG 0x4C0205C

#define mmPCIE_DBI_MSI_CAP_OFF_10H_REG 0x4C02060

#define mmPCIE_DBI_MSI_CAP_OFF_14H_REG 0x4C02064

#define mmPCIE_DBI_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG 0x4C02070

#define mmPCIE_DBI_DEVICE_CAPABILITIES_REG 0x4C02074

#define mmPCIE_DBI_DEVICE_CONTROL_DEVICE_STATUS 0x4C02078

#define mmPCIE_DBI_LINK_CAPABILITIES_REG 0x4C0207C

#define mmPCIE_DBI_LINK_CONTROL_LINK_STATUS_REG 0x4C02080

#define mmPCIE_DBI_DEVICE_CAPABILITIES2_REG 0x4C02094

#define mmPCIE_DBI_DEVICE_CONTROL2_DEVICE_STATUS2_REG 0x4C02098

#define mmPCIE_DBI_LINK_CAPABILITIES2_REG 0x4C0209C

#define mmPCIE_DBI_LINK_CONTROL2_LINK_STATUS2_REG 0x4C020A0

#define mmPCIE_DBI_PCI_MSIX_CAP_ID_NEXT_CTRL_REG 0x4C020B0

#define mmPCIE_DBI_MSIX_TABLE_OFFSET_REG 0x4C020B4

#define mmPCIE_DBI_MSIX_PBA_OFFSET_REG 0x4C020B8

#define mmPCIE_DBI_AER_EXT_CAP_HDR_OFF 0x4C02100

#define mmPCIE_DBI_UNCORR_ERR_STATUS_OFF 0x4C02104

#define mmPCIE_DBI_UNCORR_ERR_MASK_OFF 0x4C02108

#define mmPCIE_DBI_UNCORR_ERR_SEV_OFF 0x4C0210C

#define mmPCIE_DBI_CORR_ERR_STATUS_OFF 0x4C02110

Annotation

Implementation Notes