drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_masks.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_masks.h

Extension

.h

Size

9405 bytes

Lines

230

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_PCIE_DEC0_CMD_MASKS_H_
#define ASIC_REG_PCIE_DEC0_CMD_MASKS_H_

/*
 *****************************************
 *   PCIE_DEC0_CMD
 *   (Prototype: VSI_CMD)
 *****************************************
 */

/* PCIE_DEC0_CMD_SWREG0 */
#define PCIE_DEC0_CMD_SWREG0_SW_HW_VERSION_SHIFT 0
#define PCIE_DEC0_CMD_SWREG0_SW_HW_VERSION_MASK 0xFFFF
#define PCIE_DEC0_CMD_SWREG0_SW_HW_ID_SHIFT 16
#define PCIE_DEC0_CMD_SWREG0_SW_HW_ID_MASK 0xFFFF0000

/* PCIE_DEC0_CMD_SWREG1 */
#define PCIE_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_SHIFT 0
#define PCIE_DEC0_CMD_SWREG1_SW_HW_BUILDDATE_MASK 0xFFFFFFFF

/* PCIE_DEC0_CMD_SWREG2 */
#define PCIE_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_SHIFT 0
#define PCIE_DEC0_CMD_SWREG2_SW_EXT_NORM_INTR_SRC_MASK 0xFFFF
#define PCIE_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_SHIFT 16
#define PCIE_DEC0_CMD_SWREG2_SW_EXT_ABN_INTR_SRC_MASK 0xFFFF0000

/* PCIE_DEC0_CMD_SWREG3 */
#define PCIE_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_SHIFT 0
#define PCIE_DEC0_CMD_SWREG3_SW_EXE_CMDBUF_COUNT_MASK 0xFFFFFFFF

/* PCIE_DEC0_CMD_SWREG4 */
#define PCIE_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_SHIFT 0
#define PCIE_DEC0_CMD_SWREG4_SW_CMD_EXE_LSB_MASK 0xFFFFFFFF

/* PCIE_DEC0_CMD_SWREG5 */
#define PCIE_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_SHIFT 0
#define PCIE_DEC0_CMD_SWREG5_SW_CMD_EXE_MSB_MASK 0xFFFFFFFF

/* PCIE_DEC0_CMD_SWREG6 */
#define PCIE_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_SHIFT 0
#define PCIE_DEC0_CMD_SWREG6_SW_AXI_TOTALARLEN_MASK 0xFFFFFFFF

/* PCIE_DEC0_CMD_SWREG7 */
#define PCIE_DEC0_CMD_SWREG7_SW_AXI_TOTALR_SHIFT 0
#define PCIE_DEC0_CMD_SWREG7_SW_AXI_TOTALR_MASK 0xFFFFFFFF

/* PCIE_DEC0_CMD_SWREG8 */
#define PCIE_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_SHIFT 0
#define PCIE_DEC0_CMD_SWREG8_SW_AXI_TOTALAR_MASK 0xFFFFFFFF

/* PCIE_DEC0_CMD_SWREG9 */
#define PCIE_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_SHIFT 0
#define PCIE_DEC0_CMD_SWREG9_SW_AXI_TOTALRLAST_MASK 0xFFFFFFFF

/* PCIE_DEC0_CMD_SWREG10 */
#define PCIE_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_SHIFT 0
#define PCIE_DEC0_CMD_SWREG10_SW_AXI_TOTALAWLEN_MASK 0xFFFFFFFF

/* PCIE_DEC0_CMD_SWREG11 */
#define PCIE_DEC0_CMD_SWREG11_SW_AXI_TOTALW_SHIFT 0
#define PCIE_DEC0_CMD_SWREG11_SW_AXI_TOTALW_MASK 0xFFFFFFFF

/* PCIE_DEC0_CMD_SWREG12 */
#define PCIE_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_SHIFT 0
#define PCIE_DEC0_CMD_SWREG12_SW_AXI_TOTALAW_MASK 0xFFFFFFFF

/* PCIE_DEC0_CMD_SWREG13 */
#define PCIE_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_SHIFT 0
#define PCIE_DEC0_CMD_SWREG13_SW_AXI_TOTALWLAST_MASK 0xFFFFFFFF

/* PCIE_DEC0_CMD_SWREG14 */
#define PCIE_DEC0_CMD_SWREG14_SW_AXI_TOTALB_SHIFT 0
#define PCIE_DEC0_CMD_SWREG14_SW_AXI_TOTALB_MASK 0xFFFFFFFF

/* PCIE_DEC0_CMD_SWREG15 */
#define PCIE_DEC0_CMD_SWREG15_SW_WORK_STATE_SHIFT 0
#define PCIE_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK 0x7
#define PCIE_DEC0_CMD_SWREG15_RSV_SHIFT 3
#define PCIE_DEC0_CMD_SWREG15_RSV_MASK 0x3FFFF8
#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BREADY_SHIFT 22
#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BREADY_MASK 0x400000
#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BVALID_SHIFT 23
#define PCIE_DEC0_CMD_SWREG15_SW_AXI_BVALID_MASK 0x800000
#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WREADY_SHIFT 24
#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WREADY_MASK 0x1000000
#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WVALID_SHIFT 25
#define PCIE_DEC0_CMD_SWREG15_SW_AXI_WVALID_MASK 0x2000000
#define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWREADY_SHIFT 26
#define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWREADY_MASK 0x4000000
#define PCIE_DEC0_CMD_SWREG15_SW_AXI_AWVALID_SHIFT 27

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.