drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dec0_cmd_regs.h

Extension

.h

Size

1850 bytes

Lines

86

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_PCIE_DEC0_CMD_REGS_H_
#define ASIC_REG_PCIE_DEC0_CMD_REGS_H_

/*
 *****************************************
 *   PCIE_DEC0_CMD
 *   (Prototype: VSI_CMD)
 *****************************************
 */

#define mmPCIE_DEC0_CMD_SWREG0 0x4F00000

#define mmPCIE_DEC0_CMD_SWREG1 0x4F00004

#define mmPCIE_DEC0_CMD_SWREG2 0x4F00008

#define mmPCIE_DEC0_CMD_SWREG3 0x4F0000C

#define mmPCIE_DEC0_CMD_SWREG4 0x4F00010

#define mmPCIE_DEC0_CMD_SWREG5 0x4F00014

#define mmPCIE_DEC0_CMD_SWREG6 0x4F00018

#define mmPCIE_DEC0_CMD_SWREG7 0x4F0001C

#define mmPCIE_DEC0_CMD_SWREG8 0x4F00020

#define mmPCIE_DEC0_CMD_SWREG9 0x4F00024

#define mmPCIE_DEC0_CMD_SWREG10 0x4F00028

#define mmPCIE_DEC0_CMD_SWREG11 0x4F0002C

#define mmPCIE_DEC0_CMD_SWREG12 0x4F00030

#define mmPCIE_DEC0_CMD_SWREG13 0x4F00034

#define mmPCIE_DEC0_CMD_SWREG14 0x4F00038

#define mmPCIE_DEC0_CMD_SWREG15 0x4F0003C

#define mmPCIE_DEC0_CMD_SWREG16 0x4F00040

#define mmPCIE_DEC0_CMD_SWREG17 0x4F00044

#define mmPCIE_DEC0_CMD_SWREG18 0x4F00048

#define mmPCIE_DEC0_CMD_SWREG19 0x4F0004C

#define mmPCIE_DEC0_CMD_SWREG20 0x4F00050

#define mmPCIE_DEC0_CMD_SWREG21 0x4F00054

#define mmPCIE_DEC0_CMD_SWREG22 0x4F00058

#define mmPCIE_DEC0_CMD_SWREG23 0x4F0005C

#define mmPCIE_DEC0_CMD_SWREG24 0x4F00060

#define mmPCIE_DEC0_CMD_SWREG25 0x4F00064

#define mmPCIE_DEC0_CMD_SWREG26 0x4F00068

#define mmPCIE_DEC0_CMD_SWREG64 0x4F00100

#define mmPCIE_DEC0_CMD_SWREG65 0x4F00104

#define mmPCIE_DEC0_CMD_SWREG66 0x4F00108

#define mmPCIE_DEC0_CMD_SWREG67 0x4F0010C

#endif /* ASIC_REG_PCIE_DEC0_CMD_REGS_H_ */

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.