drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_regs.h
Extension
.h
Size
7299 bytes
Lines
246
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_PCIE_VDEC0_BRDG_CTRL_REGS_H_
#define ASIC_REG_PCIE_VDEC0_BRDG_CTRL_REGS_H_

/*
 *****************************************
 *   PCIE_VDEC0_BRDG_CTRL
 *   (Prototype: VDEC_BRDG_CTRL)
 *****************************************
 */

#define mmPCIE_VDEC0_BRDG_CTRL_CGM_DISABLE 0x4F03100

#define mmPCIE_VDEC0_BRDG_CTRL_IDLE_MASK 0x4F03104

#define mmPCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT 0x4F03108

#define mmPCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT 0x4F0310C

#define mmPCIE_VDEC0_BRDG_CTRL_GRACEFUL 0x4F03110

#define mmPCIE_VDEC0_BRDG_CTRL_IDLE_CGM_CNT 0x4F03114

#define mmPCIE_VDEC0_BRDG_CTRL_CAUSE_INTR 0x4F03120

#define mmPCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE 0x4F03124

#define mmPCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE 0x4F03128

#define mmPCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM 0x4F0312C

#define mmPCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK 0x4F03130

#define mmPCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK 0x4F03134

#define mmPCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK 0x4F03138

#define mmPCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK 0x4F03160

#define mmPCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK 0x4F03170

#define mmPCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK 0x4F03180

#define mmPCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK 0x4F03190

#define mmPCIE_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT 0x4F031A0

#define mmPCIE_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT 0x4F031A4

#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT 0x4F031B0

#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT 0x4F031B4

#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT 0x4F031C0

#define mmPCIE_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT 0x4F031C4

#define mmPCIE_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE 0x4F031D0

#define mmPCIE_VDEC0_BRDG_CTRL_ARC_MSG_MASK 0x4F03200

#define mmPCIE_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA 0x4F03230

#define mmPCIE_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA 0x4F03260

#define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL 0x4F03270

#define mmPCIE_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR 0x4F03280

#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L 0x4F03290

#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H 0x4F03294

#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L 0x4F032A0

#define mmPCIE_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H 0x4F032A4

#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L 0x4F032B0

#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H 0x4F032B4

#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L 0x4F032C0

#define mmPCIE_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H 0x4F032C4

#define mmPCIE_VDEC0_BRDG_CTRL_STAT_CNTR_EN 0x4F032D0

#define mmPCIE_VDEC0_BRDG_CTRL_VCD_INTR_MASK 0x4F03300

#define mmPCIE_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK 0x4F03310

Annotation

Implementation Notes