drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_ctrl_special_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_ctrl_special_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_ctrl_special_regs.h
Extension
.h
Size
5228 bytes
Lines
186
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_PCIE_VDEC0_CTRL_SPECIAL_REGS_H_
#define ASIC_REG_PCIE_VDEC0_CTRL_SPECIAL_REGS_H_

/*
 *****************************************
 *   PCIE_VDEC0_CTRL_SPECIAL
 *   (Prototype: SPECIAL_REGS)
 *****************************************
 */

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_0 0x4F04E80

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_1 0x4F04E84

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_2 0x4F04E88

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_3 0x4F04E8C

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_4 0x4F04E90

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_5 0x4F04E94

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_6 0x4F04E98

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_7 0x4F04E9C

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_8 0x4F04EA0

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_9 0x4F04EA4

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_10 0x4F04EA8

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_11 0x4F04EAC

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_12 0x4F04EB0

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_13 0x4F04EB4

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_14 0x4F04EB8

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_15 0x4F04EBC

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_16 0x4F04EC0

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_17 0x4F04EC4

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_18 0x4F04EC8

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_19 0x4F04ECC

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_20 0x4F04ED0

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_21 0x4F04ED4

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_22 0x4F04ED8

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_23 0x4F04EDC

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_24 0x4F04EE0

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_25 0x4F04EE4

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_26 0x4F04EE8

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_27 0x4F04EEC

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_28 0x4F04EF0

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_29 0x4F04EF4

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_30 0x4F04EF8

#define mmPCIE_VDEC0_CTRL_SPECIAL_GLBL_PRIV_31 0x4F04EFC

#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_GW_DATA 0x4F04F00

#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_GW_REQ 0x4F04F04

#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_NUMOF 0x4F04F0C

#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_SEL 0x4F04F10

#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_CTL 0x4F04F14

#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_MASK 0x4F04F18

#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x4F04F1C

#define mmPCIE_VDEC0_CTRL_SPECIAL_MEM_ECC_ERR_STS 0x4F04F20

Annotation

Implementation Notes