drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_wrap_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_wrap_regs.h

Extension

.h

Size

14625 bytes

Lines

602

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_PCIE_WRAP_REGS_H_
#define ASIC_REG_PCIE_WRAP_REGS_H_

/*
 *****************************************
 *   PCIE_WRAP
 *   (Prototype: PCIE_WRAP)
 *****************************************
 */

#define mmPCIE_WRAP_INTR_GEN_MASK_MIN_ADDR_0 0x4C01000

#define mmPCIE_WRAP_INTR_GEN_MASK_MIN_ADDR_1 0x4C01004

#define mmPCIE_WRAP_INTR_GEN_MASK_MAX_ADDR_0 0x4C01008

#define mmPCIE_WRAP_INTR_GEN_MASK_MAX_ADDR_1 0x4C0100C

#define mmPCIE_WRAP_INTR_GEN_MASK_TIMER 0x4C01010

#define mmPCIE_WRAP_INTR_GEN_MASK_CTRL 0x4C01014

#define mmPCIE_WRAP_MSIX_DOORBELL_OFF_ADDR 0x4C01018

#define mmPCIE_WRAP_MSIX_MASK_CTRL 0x4C0101C

#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_L_0 0x4C01020

#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_L_1 0x4C01024

#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_H_0 0x4C01028

#define mmPCIE_WRAP_PHY_FW_SRAM_ADDR_H_1 0x4C0102C

#define mmPCIE_WRAP_PHY_FW_SRAM_CFG_ADDR 0x4C01030

#define mmPCIE_WRAP_MSIX_GW 0x4C01034

#define mmPCIE_WRAP_MSIX_GW_VEC 0x4C01038

#define mmPCIE_WRAP_MSIX_GW_INTR 0x4C0103C

#define mmPCIE_WRAP_MSIX_GW_TABLE_0 0x4C01040

#define mmPCIE_WRAP_MSIX_GW_TABLE_1 0x4C01044

#define mmPCIE_WRAP_MSIX_GW_TABLE_2 0x4C01048

#define mmPCIE_WRAP_MSIX_GW_TABLE_3 0x4C0104C

#define mmPCIE_WRAP_MSIX_GW_TABLE_4 0x4C01050

#define mmPCIE_WRAP_MSIX_GW_TABLE_5 0x4C01054

#define mmPCIE_WRAP_MSIX_GW_TABLE_6 0x4C01058

#define mmPCIE_WRAP_MSIX_GW_TABLE_7 0x4C0105C

#define mmPCIE_WRAP_MSIX_GW_TABLE_8 0x4C01060

#define mmPCIE_WRAP_MSIX_GW_TABLE_9 0x4C01064

#define mmPCIE_WRAP_MSIX_GW_TABLE_10 0x4C01068

#define mmPCIE_WRAP_MSIX_GW_TABLE_11 0x4C0106C

#define mmPCIE_WRAP_MSIX_GW_TABLE_12 0x4C01070

#define mmPCIE_WRAP_MSIX_GW_TABLE_13 0x4C01074

#define mmPCIE_WRAP_MSIX_GW_TABLE_14 0x4C01078

#define mmPCIE_WRAP_MSIX_GW_TABLE_15 0x4C0107C

#define mmPCIE_WRAP_VUART_RX_0 0x4C01100

#define mmPCIE_WRAP_VUART_RX_1 0x4C01104

#define mmPCIE_WRAP_VUART_RX_2 0x4C01108

#define mmPCIE_WRAP_VUART_TX_0 0x4C0110C

#define mmPCIE_WRAP_VUART_TX_1 0x4C01110

#define mmPCIE_WRAP_VUART_TX_2 0x4C01114

#define mmPCIE_WRAP_MSI_GW_BLOCK 0x4C01120

#define mmPCIE_WRAP_PHY_FW_FSM_SIZE 0x4C0120C

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.