drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_wrap_special_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_wrap_special_regs.h

Extension

.h

Size

4718 bytes

Lines

186

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_
#define ASIC_REG_PCIE_WRAP_SPECIAL_REGS_H_

/*
 *****************************************
 *   PCIE_WRAP_SPECIAL
 *   (Prototype: SPECIAL_REGS)
 *****************************************
 */

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_0 0x4C01E80

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_1 0x4C01E84

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_2 0x4C01E88

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_3 0x4C01E8C

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_4 0x4C01E90

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_5 0x4C01E94

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_6 0x4C01E98

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_7 0x4C01E9C

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_8 0x4C01EA0

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_9 0x4C01EA4

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_10 0x4C01EA8

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_11 0x4C01EAC

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_12 0x4C01EB0

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_13 0x4C01EB4

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_14 0x4C01EB8

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_15 0x4C01EBC

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_16 0x4C01EC0

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_17 0x4C01EC4

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_18 0x4C01EC8

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_19 0x4C01ECC

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_20 0x4C01ED0

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_21 0x4C01ED4

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_22 0x4C01ED8

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_23 0x4C01EDC

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_24 0x4C01EE0

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_25 0x4C01EE4

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_26 0x4C01EE8

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_27 0x4C01EEC

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_28 0x4C01EF0

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_29 0x4C01EF4

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_30 0x4C01EF8

#define mmPCIE_WRAP_SPECIAL_GLBL_PRIV_31 0x4C01EFC

#define mmPCIE_WRAP_SPECIAL_MEM_GW_DATA 0x4C01F00

#define mmPCIE_WRAP_SPECIAL_MEM_GW_REQ 0x4C01F04

#define mmPCIE_WRAP_SPECIAL_MEM_NUMOF 0x4C01F0C

#define mmPCIE_WRAP_SPECIAL_MEM_ECC_SEL 0x4C01F10

#define mmPCIE_WRAP_SPECIAL_MEM_ECC_CTL 0x4C01F14

#define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_MASK 0x4C01F18

#define mmPCIE_WRAP_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x4C01F1C

#define mmPCIE_WRAP_SPECIAL_MEM_ECC_ERR_STS 0x4C01F20

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.