drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_core_regs.h
Extension
.h
Size
3670 bytes
Lines
158
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_PDMA0_CORE_REGS_H_
#define ASIC_REG_PDMA0_CORE_REGS_H_

/*
 *****************************************
 *   PDMA0_CORE
 *   (Prototype: DMA_CORE)
 *****************************************
 */

#define mmPDMA0_CORE_CFG_0 0x4C8B000

#define mmPDMA0_CORE_CFG_1 0x4C8B004

#define mmPDMA0_CORE_PROT 0x4C8B008

#define mmPDMA0_CORE_CKG 0x4C8B00C

#define mmPDMA0_CORE_RD_GLBL 0x4C8B07C

#define mmPDMA0_CORE_RD_HBW_MAX_OUTSTAND 0x4C8B080

#define mmPDMA0_CORE_RD_HBW_MAX_SIZE 0x4C8B084

#define mmPDMA0_CORE_RD_HBW_ARCACHE 0x4C8B088

#define mmPDMA0_CORE_RD_HBW_INFLIGHTS 0x4C8B090

#define mmPDMA0_CORE_RD_HBW_RATE_LIM_CFG 0x4C8B094

#define mmPDMA0_CORE_RD_LBW_MAX_OUTSTAND 0x4C8B0C0

#define mmPDMA0_CORE_RD_LBW_MAX_SIZE 0x4C8B0C4

#define mmPDMA0_CORE_RD_LBW_ARCACHE 0x4C8B0C8

#define mmPDMA0_CORE_RD_LBW_INFLIGHTS 0x4C8B0D0

#define mmPDMA0_CORE_RD_LBW_RATE_LIM_CFG 0x4C8B0D4

#define mmPDMA0_CORE_WR_HBW_MAX_OUTSTAND 0x4C8B100

#define mmPDMA0_CORE_WR_HBW_MAX_AWID 0x4C8B104

#define mmPDMA0_CORE_WR_HBW_AWCACHE 0x4C8B108

#define mmPDMA0_CORE_WR_HBW_INFLIGHTS 0x4C8B10C

#define mmPDMA0_CORE_WR_HBW_RATE_LIM_CFG 0x4C8B110

#define mmPDMA0_CORE_WR_LBW_MAX_OUTSTAND 0x4C8B140

#define mmPDMA0_CORE_WR_LBW_MAX_AWID 0x4C8B144

#define mmPDMA0_CORE_WR_LBW_AWCACHE 0x4C8B148

#define mmPDMA0_CORE_WR_LBW_INFLIGHTS 0x4C8B14C

#define mmPDMA0_CORE_WR_LBW_RATE_LIM_CFG 0x4C8B150

#define mmPDMA0_CORE_WR_COMP_MAX_OUTSTAND 0x4C8B180

#define mmPDMA0_CORE_WR_COMP_AWUSER 0x4C8B184

#define mmPDMA0_CORE_ERR_CFG 0x4C8B300

#define mmPDMA0_CORE_ERR_CAUSE 0x4C8B304

#define mmPDMA0_CORE_ERRMSG_ADDR_LO 0x4C8B308

#define mmPDMA0_CORE_ERRMSG_ADDR_HI 0x4C8B30C

#define mmPDMA0_CORE_ERRMSG_WDATA 0x4C8B310

#define mmPDMA0_CORE_STS0 0x4C8B380

#define mmPDMA0_CORE_STS1 0x4C8B384

#define mmPDMA0_CORE_STS_RD_CTX_SEL 0x4C8B400

#define mmPDMA0_CORE_STS_RD_CTX_SIZE 0x4C8B404

#define mmPDMA0_CORE_STS_RD_CTX_BASE_LO 0x4C8B408

#define mmPDMA0_CORE_STS_RD_CTX_BASE_HI 0x4C8B40C

#define mmPDMA0_CORE_STS_RD_CTX_ID 0x4C8B410

#define mmPDMA0_CORE_STS_RD_HB_AXI_ADDR_LO 0x4C8B414

Annotation

Implementation Notes