drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_masks.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_masks.h

File Facts

System: Linux kernel
Corpus path: drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_masks.h
Extension: .h
Size: 45224 bytes
Lines: 1166
Domain: Driver Families
Bucket: drivers/accel
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_PDMA0_QM_MASKS_H_
#define ASIC_REG_PDMA0_QM_MASKS_H_

/*
 *****************************************
 *   PDMA0_QM
 *   (Prototype: QMAN)
 *****************************************
 */

/* PDMA0_QM_GLBL_CFG0 */
#define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
#define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
#define PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 4
#define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
#define PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT 9
#define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
#define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT 14
#define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000

/* PDMA0_QM_GLBL_CFG1 */
#define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
#define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
#define PDMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4
#define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
#define PDMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 9
#define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
#define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16
#define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
#define PDMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20
#define PDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
#define PDMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25
#define PDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000

/* PDMA0_QM_GLBL_CFG2 */
#define PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_SHIFT 0
#define PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 0x1
#define PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_SHIFT 1
#define PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK 0x2
#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_SHIFT 4
#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_MASK 0x10
#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_SHIFT 5
#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_MASK 0x20
#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_SHIFT 6
#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_MASK 0x40
#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_SHIFT 7
#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_MASK 0x80
#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_SHIFT 8
#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_MASK 0x100
#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_SHIFT 9
#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_MASK 0x200
#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_SHIFT 10
#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_MASK 0x400
#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_SHIFT 11
#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_MASK 0x800
#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_SHIFT 12
#define PDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_MASK 0x1000
#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_SHIFT 13
#define PDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_MASK 0x2000
#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_SHIFT 14
#define PDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_MASK 0x4000
#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_SHIFT 15
#define PDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_MASK 0x8000
#define PDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_SHIFT 16
#define PDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_MASK 0x10000

/* PDMA0_QM_GLBL_ERR_CFG */
#define PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0
#define PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF
#define PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4
#define PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0
#define PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9
#define PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00
#define PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16
#define PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000
#define PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20
#define PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000
#define PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25
#define PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000
#define PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31
#define PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000

/* PDMA0_QM_GLBL_ERR_CFG1 */
#define PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT 0
#define PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_MASK 0x1
#define PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT 1
#define PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_MASK 0x2
#define PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT 2
#define PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_MASK 0x4

Annotation

Atlas domain: Driver Families / drivers/accel.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.