drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_etr_masks.h
Extension
.h
Size
10146 bytes
Lines
312
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_PSOC_ETR_MASKS_H_
#define ASIC_REG_PSOC_ETR_MASKS_H_

/*
 *****************************************
 *   PSOC_ETR
 *   (Prototype: ETR)
 *****************************************
 */

/* PSOC_ETR_RSZ */
#define PSOC_ETR_RSZ_RSZ_ETR_SHIFT 0
#define PSOC_ETR_RSZ_RSZ_ETR_MASK 0x7FFFFFFF

/* PSOC_ETR_STS */
#define PSOC_ETR_STS_FULL_SHIFT 0
#define PSOC_ETR_STS_FULL_MASK 0x1
#define PSOC_ETR_STS_TRIGGERED_SHIFT 1
#define PSOC_ETR_STS_TRIGGERED_MASK 0x2
#define PSOC_ETR_STS_TMCREADY_SHIFT 2
#define PSOC_ETR_STS_TMCREADY_MASK 0x4
#define PSOC_ETR_STS_FTEMPTY_SHIFT 3
#define PSOC_ETR_STS_FTEMPTY_MASK 0x8
#define PSOC_ETR_STS_EMPTY_SHIFT 4
#define PSOC_ETR_STS_EMPTY_MASK 0x10
#define PSOC_ETR_STS_MEMERR_SHIFT 5
#define PSOC_ETR_STS_MEMERR_MASK 0x20

/* PSOC_ETR_RRD */
#define PSOC_ETR_RRD_RRD_SHIFT 0
#define PSOC_ETR_RRD_RRD_MASK 0xFFFFFFFF

/* PSOC_ETR_RRP */
#define PSOC_ETR_RRP_RRP_SHIFT 0
#define PSOC_ETR_RRP_RRP_MASK 0xFFFFFFFF

/* PSOC_ETR_RWP */
#define PSOC_ETR_RWP_RWP_SHIFT 0
#define PSOC_ETR_RWP_RWP_MASK 0xFFFFFFFF

/* PSOC_ETR_TRG */
#define PSOC_ETR_TRG_TRG_SHIFT 0
#define PSOC_ETR_TRG_TRG_MASK 0xFFFFFFFF

/* PSOC_ETR_CTL */
#define PSOC_ETR_CTL_TRACECAPTEN_SHIFT 0
#define PSOC_ETR_CTL_TRACECAPTEN_MASK 0x1

/* PSOC_ETR_RWD */
#define PSOC_ETR_RWD_RWD_SHIFT 0
#define PSOC_ETR_RWD_RWD_MASK 0xFFFFFFFF

/* PSOC_ETR_MODE */
#define PSOC_ETR_MODE_MODE_SHIFT 0
#define PSOC_ETR_MODE_MODE_MASK 0x3

/* PSOC_ETR_LBUFLEVEL */
#define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_SHIFT 0
#define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_MASK 0x7FFFFFFF

/* PSOC_ETR_CBUFLEVEL */
#define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_SHIFT 0
#define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_MASK 0x7FFFFFFF

/* PSOC_ETR_BUFWM */
#define PSOC_ETR_BUFWM_BUFWM_SHIFT 0
#define PSOC_ETR_BUFWM_BUFWM_MASK 0x3FFFFFFF

/* PSOC_ETR_RRPHI */
#define PSOC_ETR_RRPHI_RRPHI_SHIFT 0
#define PSOC_ETR_RRPHI_RRPHI_MASK 0xFF

/* PSOC_ETR_RWPHI */
#define PSOC_ETR_RWPHI_RWPHI_SHIFT 0
#define PSOC_ETR_RWPHI_RWPHI_MASK 0xFF

/* PSOC_ETR_AXICTL */
#define PSOC_ETR_AXICTL_PROTCTRLBIT0_SHIFT 0
#define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1
#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1
#define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2
#define PSOC_ETR_AXICTL_CACHECTRLBIT0_SHIFT 2
#define PSOC_ETR_AXICTL_CACHECTRLBIT0_MASK 0x4
#define PSOC_ETR_AXICTL_CACHECTRLBIT1_SHIFT 3
#define PSOC_ETR_AXICTL_CACHECTRLBIT1_MASK 0x8
#define PSOC_ETR_AXICTL_CACHECTRLBIT2_SHIFT 4
#define PSOC_ETR_AXICTL_CACHECTRLBIT2_MASK 0x10
#define PSOC_ETR_AXICTL_CACHECTRLBIT3_SHIFT 5
#define PSOC_ETR_AXICTL_CACHECTRLBIT3_MASK 0x20
#define PSOC_ETR_AXICTL_SCATTERGATHERMODE_SHIFT 7

Annotation

Implementation Notes