drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h

Extension

.h

Size

65347 bytes

Lines

1398

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_
#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_

/*
 *****************************************
 *   PSOC_GLOBAL_CONF
 *   (Prototype: GLOBAL_CONF)
 *****************************************
 */

/* PSOC_GLOBAL_CONF_NON_RST_FLOPS */
#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_PCI_FW_FSM */
#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0
#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1

/* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_SHIFT 4
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_MASK 0x10
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_SHIFT 5
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_MASK 0x20
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_SHIFT 6
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_MASK 0x40
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_SHIFT 7
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_MASK 0x80
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_PRST_RST_IND_SHIFT 8
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_PRST_RST_IND_MASK 0x100
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FLR_RST_IND_SHIFT 9
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FLR_RST_IND_MASK 0x200
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FW_RST_IND_SHIFT 10
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_FW_RST_IND_MASK 0x400
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_ECC_DERR_RST_IND_SHIFT 11
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_ECC_DERR_RST_IND_MASK 0x800

/* PSOC_GLOBAL_CONF_BTM_FSM */
#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0
#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0x1F

/* PSOC_GLOBAL_CONF_BTL_ROM_DELAY */
#define PSOC_GLOBAL_CONF_BTL_ROM_DELAY_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_BTL_ROM_DELAY_VAL_MASK 0xFFFF

/* PSOC_GLOBAL_CONF_SW_BTM_FSM */
#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0
#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0x1F

/* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */
#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT 0
#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK 0x1F

/* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */
#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK 0xFFFFFFFF

/* PSOC_GLOBAL_CONF_QSPI_SPI */
#define PSOC_GLOBAL_CONF_QSPI_SPI_SEL_SHIFT 0
#define PSOC_GLOBAL_CONF_QSPI_SPI_SEL_MASK 0x1

/* PSOC_GLOBAL_CONF_SPI_MEM_EN */
#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SPI_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SPI_MASK 0x1
#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_QSPI_SHIFT 1
#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_QSPI_MASK 0x2

/* PSOC_GLOBAL_CONF_PRSTN */
#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT 0
#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1

/* PSOC_GLOBAL_CONF_PCIE_EN */
#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT 0
#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1

/* PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR */
#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_SHIFT 0
#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK 0x1

/* PSOC_GLOBAL_CONF_SPI_IMG_STS */
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_PRI_SHIFT 0
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_PRI_MASK 0x3
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_SEC_SHIFT 2
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SPI_SEC_MASK 0xC
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_PRI_SHIFT 4
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_PRI_MASK 0x30
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SEC_SHIFT 6
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SEC_MASK 0xC0
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCIE_PRI_SHIFT 8

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.