drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_masks.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_masks.h

Extension

.h

Size

100195 bytes

Lines

2322

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_PSOC_RESET_CONF_MASKS_H_
#define ASIC_REG_PSOC_RESET_CONF_MASKS_H_

/*
 *****************************************
 *   PSOC_RESET_CONF
 *   (Prototype: PSOC_RESET_CONF)
 *****************************************
 */

/* PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG */
#define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_PSOC_SOFT_RST_CFG */
#define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_PSOC_FW_RST_CFG */
#define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_PSOC_WD_RST_CFG */
#define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_PSOC_MNL_RST_CFG */
#define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_PSOC_FLR_RST_CFG */
#define PSOC_RESET_CONF_PSOC_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_FLR_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG */
#define PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_PSOC_SW_RST_CFG */
#define PSOC_RESET_CONF_PSOC_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_PSOC_SW_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_CPU_PRSTN_RST_CFG */
#define PSOC_RESET_CONF_CPU_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_PRSTN_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_CPU_SOFT_RST_CFG */
#define PSOC_RESET_CONF_CPU_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_SOFT_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_CPU_FW_RST_CFG */
#define PSOC_RESET_CONF_CPU_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_FW_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_CPU_WD_RST_CFG */
#define PSOC_RESET_CONF_CPU_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_WD_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_CPU_MNL_RST_CFG */
#define PSOC_RESET_CONF_CPU_MNL_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_MNL_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_CPU_FLR_RST_CFG */
#define PSOC_RESET_CONF_CPU_FLR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_FLR_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG */
#define PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_CPU_SW_RST_CFG */
#define PSOC_RESET_CONF_CPU_SW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_CPU_SW_RST_CFG_EN_MASK 0x1

/* PSOC_RESET_CONF_ARC_PRSTN_RST_CFG */
#define PSOC_RESET_CONF_ARC_PRSTN_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_PRSTN_RST_CFG_EN_MASK 0x3

/* PSOC_RESET_CONF_ARC_SOFT_RST_CFG */
#define PSOC_RESET_CONF_ARC_SOFT_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_SOFT_RST_CFG_EN_MASK 0x3

/* PSOC_RESET_CONF_ARC_FW_RST_CFG */
#define PSOC_RESET_CONF_ARC_FW_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_FW_RST_CFG_EN_MASK 0x3

/* PSOC_RESET_CONF_ARC_WD_RST_CFG */
#define PSOC_RESET_CONF_ARC_WD_RST_CFG_EN_SHIFT 0
#define PSOC_RESET_CONF_ARC_WD_RST_CFG_EN_MASK 0x3

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.