drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_regs.h

Extension

.h

Size

27900 bytes

Lines

990

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_PSOC_RESET_CONF_REGS_H_
#define ASIC_REG_PSOC_RESET_CONF_REGS_H_

/*
 *****************************************
 *   PSOC_RESET_CONF
 *   (Prototype: PSOC_RESET_CONF)
 *****************************************
 */

#define mmPSOC_RESET_CONF_PSOC_PRSTN_RST_CFG 0x4C74000

#define mmPSOC_RESET_CONF_PSOC_SOFT_RST_CFG 0x4C74004

#define mmPSOC_RESET_CONF_PSOC_FW_RST_CFG 0x4C74008

#define mmPSOC_RESET_CONF_PSOC_WD_RST_CFG 0x4C7400C

#define mmPSOC_RESET_CONF_PSOC_MNL_RST_CFG 0x4C74010

#define mmPSOC_RESET_CONF_PSOC_FLR_RST_CFG 0x4C74014

#define mmPSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG 0x4C74018

#define mmPSOC_RESET_CONF_PSOC_SW_RST_CFG 0x4C7401C

#define mmPSOC_RESET_CONF_CPU_PRSTN_RST_CFG 0x4C74020

#define mmPSOC_RESET_CONF_CPU_SOFT_RST_CFG 0x4C74024

#define mmPSOC_RESET_CONF_CPU_FW_RST_CFG 0x4C74028

#define mmPSOC_RESET_CONF_CPU_WD_RST_CFG 0x4C7402C

#define mmPSOC_RESET_CONF_CPU_MNL_RST_CFG 0x4C74030

#define mmPSOC_RESET_CONF_CPU_FLR_RST_CFG 0x4C74034

#define mmPSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG 0x4C74038

#define mmPSOC_RESET_CONF_CPU_SW_RST_CFG 0x4C7403C

#define mmPSOC_RESET_CONF_ARC_PRSTN_RST_CFG 0x4C74040

#define mmPSOC_RESET_CONF_ARC_SOFT_RST_CFG 0x4C74044

#define mmPSOC_RESET_CONF_ARC_FW_RST_CFG 0x4C74048

#define mmPSOC_RESET_CONF_ARC_WD_RST_CFG 0x4C7404C

#define mmPSOC_RESET_CONF_ARC_MNL_RST_CFG 0x4C74050

#define mmPSOC_RESET_CONF_ARC_FLR_RST_CFG 0x4C74054

#define mmPSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG 0x4C74058

#define mmPSOC_RESET_CONF_ARC_SW_RST_CFG 0x4C7405C

#define mmPSOC_RESET_CONF_SIF_PRSTN_RST_CFG 0x4C74060

#define mmPSOC_RESET_CONF_SIF_SOFT_RST_CFG 0x4C74064

#define mmPSOC_RESET_CONF_SIF_FW_RST_CFG 0x4C74068

#define mmPSOC_RESET_CONF_SIF_WD_RST_CFG 0x4C7406C

#define mmPSOC_RESET_CONF_SIF_MNL_RST_CFG 0x4C74070

#define mmPSOC_RESET_CONF_SIF_FLR_RST_CFG 0x4C74074

#define mmPSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG 0x4C74078

#define mmPSOC_RESET_CONF_SIF_SW_RST_CFG 0x4C7407C

#define mmPSOC_RESET_CONF_SRAM_PRSTN_RST_CFG 0x4C74080

#define mmPSOC_RESET_CONF_SRAM_SOFT_RST_CFG 0x4C74084

#define mmPSOC_RESET_CONF_SRAM_FW_RST_CFG 0x4C74088

#define mmPSOC_RESET_CONF_SRAM_WD_RST_CFG 0x4C7408C

#define mmPSOC_RESET_CONF_SRAM_MNL_RST_CFG 0x4C74090

#define mmPSOC_RESET_CONF_SRAM_FLR_RST_CFG 0x4C74094

#define mmPSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG 0x4C74098

#define mmPSOC_RESET_CONF_SRAM_SW_RST_CFG 0x4C7409C

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.