drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_masks.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_masks.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_masks.h
Extension
.h
Size
9894 bytes
Lines
314
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_ROT0_MASKS_H_
#define ASIC_REG_ROT0_MASKS_H_

/*
 *****************************************
 *   ROT0
 *   (Prototype: ROTATOR)
 *****************************************
 */

/* ROT0_KMD_MODE */
#define ROT0_KMD_MODE_EN_SHIFT 0
#define ROT0_KMD_MODE_EN_MASK 0x1

/* ROT0_CPL_QUEUE_EN */
#define ROT0_CPL_QUEUE_EN_Q_EN_SHIFT 0
#define ROT0_CPL_QUEUE_EN_Q_EN_MASK 0x1

/* ROT0_CPL_QUEUE_ADDR_L */
#define ROT0_CPL_QUEUE_ADDR_L_VAL_SHIFT 0
#define ROT0_CPL_QUEUE_ADDR_L_VAL_MASK 0xFFFFFFFF

/* ROT0_CPL_QUEUE_ADDR_H */
#define ROT0_CPL_QUEUE_ADDR_H_VAL_SHIFT 0
#define ROT0_CPL_QUEUE_ADDR_H_VAL_MASK 0xFFFFFFFF

/* ROT0_CPL_QUEUE_DATA */
#define ROT0_CPL_QUEUE_DATA_VAL_SHIFT 0
#define ROT0_CPL_QUEUE_DATA_VAL_MASK 0xFFFFFFFF

/* ROT0_CPL_QUEUE_AWUSER */
#define ROT0_CPL_QUEUE_AWUSER_VAL_SHIFT 0
#define ROT0_CPL_QUEUE_AWUSER_VAL_MASK 0xFFFFFFFF

/* ROT0_CPL_QUEUE_AXI */
#define ROT0_CPL_QUEUE_AXI_CACHE_SHIFT 0
#define ROT0_CPL_QUEUE_AXI_CACHE_MASK 0xF
#define ROT0_CPL_QUEUE_AXI_PROT_SHIFT 4
#define ROT0_CPL_QUEUE_AXI_PROT_MASK 0x70

/* ROT0_CPL_MSG_THRESHOLD */
#define ROT0_CPL_MSG_THRESHOLD_VAL_SHIFT 0
#define ROT0_CPL_MSG_THRESHOLD_VAL_MASK 0x3F

/* ROT0_CPL_MSG_AXI */
#define ROT0_CPL_MSG_AXI_CACHE_SHIFT 0
#define ROT0_CPL_MSG_AXI_CACHE_MASK 0xF
#define ROT0_CPL_MSG_AXI_PROT_SHIFT 4
#define ROT0_CPL_MSG_AXI_PROT_MASK 0x70

/* ROT0_AXI_WB */
#define ROT0_AXI_WB_CACHE_SHIFT 0
#define ROT0_AXI_WB_CACHE_MASK 0xF
#define ROT0_AXI_WB_PROT_SHIFT 4
#define ROT0_AXI_WB_PROT_MASK 0x70

/* ROT0_ERR_CFG */
#define ROT0_ERR_CFG_STOP_ON_ERR_SHIFT 0
#define ROT0_ERR_CFG_STOP_ON_ERR_MASK 0x1

/* ROT0_ERR_STATUS */
#define ROT0_ERR_STATUS_ROT_HBW_RD_SHIFT 0
#define ROT0_ERR_STATUS_ROT_HBW_RD_MASK 0x1
#define ROT0_ERR_STATUS_ROT_HBW_WR_SHIFT 1
#define ROT0_ERR_STATUS_ROT_HBW_WR_MASK 0x2
#define ROT0_ERR_STATUS_QMAN_HBW_RD_SHIFT 2
#define ROT0_ERR_STATUS_QMAN_HBW_RD_MASK 0x4
#define ROT0_ERR_STATUS_QMAN_HBW_WR_SHIFT 3
#define ROT0_ERR_STATUS_QMAN_HBW_WR_MASK 0x8
#define ROT0_ERR_STATUS_ROT_LBW_WR_SHIFT 4
#define ROT0_ERR_STATUS_ROT_LBW_WR_MASK 0x10

/* ROT0_WBC_MAX_OUTSTANDING */
#define ROT0_WBC_MAX_OUTSTANDING_VAL_SHIFT 0
#define ROT0_WBC_MAX_OUTSTANDING_VAL_MASK 0xFFFF

/* ROT0_WBC_RL */
#define ROT0_WBC_RL_SATURATION_SHIFT 0
#define ROT0_WBC_RL_SATURATION_MASK 0xFF
#define ROT0_WBC_RL_TIMEOUT_SHIFT 8
#define ROT0_WBC_RL_TIMEOUT_MASK 0xFF00
#define ROT0_WBC_RL_RST_TOKEN_SHIFT 16
#define ROT0_WBC_RL_RST_TOKEN_MASK 0xFF0000
#define ROT0_WBC_RL_RATE_LIMITER_EN_SHIFT 24
#define ROT0_WBC_RL_RATE_LIMITER_EN_MASK 0x1000000

/* ROT0_WBC_INFLIGHTS */
#define ROT0_WBC_INFLIGHTS_VAL_SHIFT 0
#define ROT0_WBC_INFLIGHTS_VAL_MASK 0xFFFF

Annotation

Implementation Notes