drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_arc_aux_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_arc_aux_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/rot0_qm_arc_aux_regs.h
Extension
.h
Size
16439 bytes
Lines
592
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_
#define ASIC_REG_ROT0_QM_ARC_AUX_REGS_H_

/*
 *****************************************
 *   ROT0_QM_ARC_AUX
 *   (Prototype: QMAN_ARC_AUX)
 *****************************************
 */

#define mmROT0_QM_ARC_AUX_RUN_HALT_REQ 0x4E08100

#define mmROT0_QM_ARC_AUX_RUN_HALT_ACK 0x4E08104

#define mmROT0_QM_ARC_AUX_RST_VEC_ADDR 0x4E08108

#define mmROT0_QM_ARC_AUX_DBG_MODE 0x4E0810C

#define mmROT0_QM_ARC_AUX_CLUSTER_NUM 0x4E08110

#define mmROT0_QM_ARC_AUX_ARC_NUM 0x4E08114

#define mmROT0_QM_ARC_AUX_WAKE_UP_EVENT 0x4E08118

#define mmROT0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x4E0811C

#define mmROT0_QM_ARC_AUX_CTI_AP_STS 0x4E08120

#define mmROT0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4E08124

#define mmROT0_QM_ARC_AUX_ARC_RST 0x4E08128

#define mmROT0_QM_ARC_AUX_ARC_RST_REQ 0x4E0812C

#define mmROT0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4E08130

#define mmROT0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4E08134

#define mmROT0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4E08138

#define mmROT0_QM_ARC_AUX_PCIE_MSB_ADDR 0x4E0813C

#define mmROT0_QM_ARC_AUX_CFG_LSB_ADDR 0x4E08140

#define mmROT0_QM_ARC_AUX_CFG_MSB_ADDR 0x4E08144

#define mmROT0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4E08150

#define mmROT0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4E08154

#define mmROT0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4E08158

#define mmROT0_QM_ARC_AUX_HBM1_MSB_ADDR 0x4E0815C

#define mmROT0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4E08160

#define mmROT0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4E08164

#define mmROT0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4E08168

#define mmROT0_QM_ARC_AUX_HBM3_MSB_ADDR 0x4E0816C

#define mmROT0_QM_ARC_AUX_HBM0_OFFSET 0x4E08170

#define mmROT0_QM_ARC_AUX_HBM1_OFFSET 0x4E08174

#define mmROT0_QM_ARC_AUX_HBM2_OFFSET 0x4E08178

#define mmROT0_QM_ARC_AUX_HBM3_OFFSET 0x4E0817C

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4E08180

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4E08184

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4E08188

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x4E0818C

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4E08190

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4E08194

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4E08198

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x4E0819C

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x4E081A0

#define mmROT0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x4E081A4

Annotation

Implementation Notes