drivers/accel/habanalabs/include/gaudi2/asic_reg/xbar_edge_0_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/xbar_edge_0_regs.h

Extension

.h

Size

4834 bytes

Lines

200

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_XBAR_EDGE_0_REGS_H_
#define ASIC_REG_XBAR_EDGE_0_REGS_H_

/*
 *****************************************
 *   XBAR_EDGE_0
 *   (Prototype: XBAR)
 *****************************************
 */

#define mmXBAR_EDGE_0_LBW_HIF0_BASE_ADDR 0x4D48000

#define mmXBAR_EDGE_0_LBW_HIF0_ADDR_MASK 0x4D48004

#define mmXBAR_EDGE_0_LBW_HIF1_BASE_ADDR 0x4D48008

#define mmXBAR_EDGE_0_LBW_HIF1_ADDR_MASK 0x4D4800C

#define mmXBAR_EDGE_0_LBW_HMMU0_BASE_ADDR 0x4D48010

#define mmXBAR_EDGE_0_LBW_HMMU0_ADDR_MASK 0x4D48014

#define mmXBAR_EDGE_0_LBW_HMMU1_BASE_ADDR 0x4D48018

#define mmXBAR_EDGE_0_LBW_HMMU1_ADDR_MASK 0x4D4801C

#define mmXBAR_EDGE_0_LBW_EDMA_BASE_ADDR0 0x4D48020

#define mmXBAR_EDGE_0_LBW_EDMA_ADDR_MASK0 0x4D48024

#define mmXBAR_EDGE_0_LBW_EDMA_BASE_ADDR1 0x4D48028

#define mmXBAR_EDGE_0_LBW_EDMA_ADDR_MASK1 0x4D4802C

#define mmXBAR_EDGE_0_LBW_HBM_BASE_ADDR0 0x4D48030

#define mmXBAR_EDGE_0_LBW_HBM_ADDR_MASK0 0x4D48034

#define mmXBAR_EDGE_0_LBW_HBM_BASE_ADDR1 0x4D48038

#define mmXBAR_EDGE_0_LBW_HBM_ADDR_MASK1 0x4D4803C

#define mmXBAR_EDGE_0_LBW_XBAR_BASE_ADDR0 0x4D48040

#define mmXBAR_EDGE_0_LBW_XBAR_ADDR_MASK0 0x4D48044

#define mmXBAR_EDGE_0_LBW_XBAR_BASE_ADDR1 0x4D48048

#define mmXBAR_EDGE_0_LBW_XBAR_ADDR_MASK1 0x4D4804C

#define mmXBAR_EDGE_0_DBG_HIF0_BASE_ADDR 0x4D48080

#define mmXBAR_EDGE_0_DBG_HIF0_ADDR_MASK 0x4D48084

#define mmXBAR_EDGE_0_DBG_HIF1_BASE_ADDR 0x4D48088

#define mmXBAR_EDGE_0_DBG_HIF1_ADDR_MASK 0x4D4808C

#define mmXBAR_EDGE_0_DBG_HMMU0_BASE_ADDR 0x4D48090

#define mmXBAR_EDGE_0_DBG_HMMU0_ADDR_MASK 0x4D48094

#define mmXBAR_EDGE_0_DBG_HMMU1_BASE_ADDR 0x4D48098

#define mmXBAR_EDGE_0_DBG_HMMU1_ADDR_MASK 0x4D4809C

#define mmXBAR_EDGE_0_DBG_EDMA_BASE_ADDR0 0x4D480A0

#define mmXBAR_EDGE_0_DBG_EDMA_ADDR_MASK0 0x4D480A4

#define mmXBAR_EDGE_0_DBG_EDMA_BASE_ADDR1 0x4D480A8

#define mmXBAR_EDGE_0_DBG_EDMA_ADDR_MASK1 0x4D480AC

#define mmXBAR_EDGE_0_DBG_HBM_BASE_ADDR0 0x4D480B0

#define mmXBAR_EDGE_0_DBG_HBM_ADDR_MASK0 0x4D480B4

#define mmXBAR_EDGE_0_DBG_HBM_BASE_ADDR1 0x4D480B8

#define mmXBAR_EDGE_0_DBG_HBM_ADDR_MASK1 0x4D480BC

#define mmXBAR_EDGE_0_DBG_XBAR_BASE_ADDR0 0x4D480C0

#define mmXBAR_EDGE_0_DBG_XBAR_ADDR_MASK0 0x4D480C4

#define mmXBAR_EDGE_0_DBG_XBAR_BASE_ADDR1 0x4D480C8

#define mmXBAR_EDGE_0_DBG_XBAR_ADDR_MASK1 0x4D480CC

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.