drivers/accel/habanalabs/include/gaudi2/asic_reg/xbar_mid_0_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/xbar_mid_0_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/xbar_mid_0_regs.h
Extension
.h
Size
4742 bytes
Lines
200
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_XBAR_MID_0_REGS_H_
#define ASIC_REG_XBAR_MID_0_REGS_H_

/*
 *****************************************
 *   XBAR_MID_0
 *   (Prototype: XBAR)
 *****************************************
 */

#define mmXBAR_MID_0_LBW_HIF0_BASE_ADDR 0x4D40000

#define mmXBAR_MID_0_LBW_HIF0_ADDR_MASK 0x4D40004

#define mmXBAR_MID_0_LBW_HIF1_BASE_ADDR 0x4D40008

#define mmXBAR_MID_0_LBW_HIF1_ADDR_MASK 0x4D4000C

#define mmXBAR_MID_0_LBW_HMMU0_BASE_ADDR 0x4D40010

#define mmXBAR_MID_0_LBW_HMMU0_ADDR_MASK 0x4D40014

#define mmXBAR_MID_0_LBW_HMMU1_BASE_ADDR 0x4D40018

#define mmXBAR_MID_0_LBW_HMMU1_ADDR_MASK 0x4D4001C

#define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR0 0x4D40020

#define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK0 0x4D40024

#define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR1 0x4D40028

#define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK1 0x4D4002C

#define mmXBAR_MID_0_LBW_HBM_BASE_ADDR0 0x4D40030

#define mmXBAR_MID_0_LBW_HBM_ADDR_MASK0 0x4D40034

#define mmXBAR_MID_0_LBW_HBM_BASE_ADDR1 0x4D40038

#define mmXBAR_MID_0_LBW_HBM_ADDR_MASK1 0x4D4003C

#define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR0 0x4D40040

#define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK0 0x4D40044

#define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR1 0x4D40048

#define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK1 0x4D4004C

#define mmXBAR_MID_0_DBG_HIF0_BASE_ADDR 0x4D40080

#define mmXBAR_MID_0_DBG_HIF0_ADDR_MASK 0x4D40084

#define mmXBAR_MID_0_DBG_HIF1_BASE_ADDR 0x4D40088

#define mmXBAR_MID_0_DBG_HIF1_ADDR_MASK 0x4D4008C

#define mmXBAR_MID_0_DBG_HMMU0_BASE_ADDR 0x4D40090

#define mmXBAR_MID_0_DBG_HMMU0_ADDR_MASK 0x4D40094

#define mmXBAR_MID_0_DBG_HMMU1_BASE_ADDR 0x4D40098

#define mmXBAR_MID_0_DBG_HMMU1_ADDR_MASK 0x4D4009C

#define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR0 0x4D400A0

#define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK0 0x4D400A4

#define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR1 0x4D400A8

#define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK1 0x4D400AC

#define mmXBAR_MID_0_DBG_HBM_BASE_ADDR0 0x4D400B0

#define mmXBAR_MID_0_DBG_HBM_ADDR_MASK0 0x4D400B4

#define mmXBAR_MID_0_DBG_HBM_BASE_ADDR1 0x4D400B8

#define mmXBAR_MID_0_DBG_HBM_ADDR_MASK1 0x4D400BC

#define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR0 0x4D400C0

#define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK0 0x4D400C4

#define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR1 0x4D400C8

#define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK1 0x4D400CC

Annotation

Implementation Notes