drivers/accel/habanalabs/include/gaudi2/gaudi2_async_events.h
Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/gaudi2_async_events.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/habanalabs/include/gaudi2/gaudi2_async_events.h- Extension
.h- Size
- 36732 bytes
- Lines
- 973
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
enum gaudi2_async_event_id
Annotated Snippet
#ifndef __GAUDI2_ASYNC_EVENTS_H_
#define __GAUDI2_ASYNC_EVENTS_H_
enum gaudi2_async_event_id {
GAUDI2_EVENT_PCIE_CORE_SERR = 32,
GAUDI2_EVENT_PCIE_CORE_DERR = 33,
GAUDI2_EVENT_PCIE_IF_SERR = 34,
GAUDI2_EVENT_PCIE_IF_DERR = 35,
GAUDI2_EVENT_PCIE_PHY_SERR = 36,
GAUDI2_EVENT_PCIE_PHY_DERR = 37,
GAUDI2_EVENT_TPC0_ECC_SERR = 38,
GAUDI2_EVENT_TPC1_ECC_SERR = 39,
GAUDI2_EVENT_TPC2_ECC_SERR = 40,
GAUDI2_EVENT_TPC3_ECC_SERR = 41,
GAUDI2_EVENT_TPC4_ECC_SERR = 42,
GAUDI2_EVENT_TPC5_ECC_SERR = 43,
GAUDI2_EVENT_TPC6_ECC_SERR = 44,
GAUDI2_EVENT_TPC7_ECC_SERR = 45,
GAUDI2_EVENT_TPC8_ECC_SERR = 46,
GAUDI2_EVENT_TPC9_ECC_SERR = 47,
GAUDI2_EVENT_TPC10_ECC_SERR = 48,
GAUDI2_EVENT_TPC11_ECC_SERR = 49,
GAUDI2_EVENT_TPC12_ECC_SERR = 50,
GAUDI2_EVENT_TPC13_ECC_SERR = 51,
GAUDI2_EVENT_TPC14_ECC_SERR = 52,
GAUDI2_EVENT_TPC15_ECC_SERR = 53,
GAUDI2_EVENT_TPC16_ECC_SERR = 54,
GAUDI2_EVENT_TPC17_ECC_SERR = 55,
GAUDI2_EVENT_TPC18_ECC_SERR = 56,
GAUDI2_EVENT_TPC19_ECC_SERR = 57,
GAUDI2_EVENT_TPC20_ECC_SERR = 58,
GAUDI2_EVENT_TPC21_ECC_SERR = 59,
GAUDI2_EVENT_TPC22_ECC_SERR = 60,
GAUDI2_EVENT_TPC23_ECC_SERR = 61,
GAUDI2_EVENT_TPC24_ECC_SERR = 62,
GAUDI2_EVENT_TPC0_ECC_DERR = 63,
GAUDI2_EVENT_TPC1_ECC_DERR = 64,
GAUDI2_EVENT_TPC2_ECC_DERR = 65,
GAUDI2_EVENT_TPC3_ECC_DERR = 66,
GAUDI2_EVENT_TPC4_ECC_DERR = 67,
GAUDI2_EVENT_TPC5_ECC_DERR = 68,
GAUDI2_EVENT_TPC6_ECC_DERR = 69,
GAUDI2_EVENT_TPC7_ECC_DERR = 70,
GAUDI2_EVENT_TPC8_ECC_DERR = 71,
GAUDI2_EVENT_TPC9_ECC_DERR = 72,
GAUDI2_EVENT_TPC10_ECC_DERR = 73,
GAUDI2_EVENT_TPC11_ECC_DERR = 74,
GAUDI2_EVENT_TPC12_ECC_DERR = 75,
GAUDI2_EVENT_TPC13_ECC_DERR = 76,
GAUDI2_EVENT_TPC14_ECC_DERR = 77,
GAUDI2_EVENT_TPC15_ECC_DERR = 78,
GAUDI2_EVENT_TPC16_ECC_DERR = 79,
GAUDI2_EVENT_TPC17_ECC_DERR = 80,
GAUDI2_EVENT_TPC18_ECC_DERR = 81,
GAUDI2_EVENT_TPC19_ECC_DERR = 82,
GAUDI2_EVENT_TPC20_ECC_DERR = 83,
GAUDI2_EVENT_TPC21_ECC_DERR = 84,
GAUDI2_EVENT_TPC22_ECC_DERR = 85,
GAUDI2_EVENT_TPC23_ECC_DERR = 86,
GAUDI2_EVENT_TPC24_ECC_DERR = 87,
GAUDI2_EVENT_MME0_SBTE0_ECC_SERR = 88,
GAUDI2_EVENT_MME0_SBTE1_ECC_SERR = 89,
GAUDI2_EVENT_MME0_SBTE2_ECC_SERR = 90,
GAUDI2_EVENT_MME0_SBTE3_ECC_SERR = 91,
GAUDI2_EVENT_MME0_SBTE4_ECC_SERR = 92,
GAUDI2_EVENT_MME0_CTRL_ECC_SERR = 93,
GAUDI2_EVENT_MME0_WAP_ECC_SERR = 94,
GAUDI2_EVENT_MME1_SBTE0_ECC_SERR = 95,
GAUDI2_EVENT_MME1_SBTE1_ECC_SERR = 96,
GAUDI2_EVENT_MME1_SBTE2_ECC_SERR = 97,
GAUDI2_EVENT_MME1_SBTE3_ECC_SERR = 98,
GAUDI2_EVENT_MME1_SBTE4_ECC_SERR = 99,
GAUDI2_EVENT_MME1_CTRL_ECC_SERR = 100,
GAUDI2_EVENT_MME1_WAP_ECC_SERR = 101,
GAUDI2_EVENT_MME2_SBTE0_ECC_SERR = 102,
GAUDI2_EVENT_MME2_SBTE1_ECC_SERR = 103,
GAUDI2_EVENT_MME2_SBTE2_ECC_SERR = 104,
GAUDI2_EVENT_MME2_SBTE3_ECC_SERR = 105,
GAUDI2_EVENT_MME2_SBTE4_ECC_SERR = 106,
GAUDI2_EVENT_MME2_CTRL_ECC_SERR = 107,
GAUDI2_EVENT_MME2_WAP_ECC_SERR = 108,
GAUDI2_EVENT_MME3_SBTE0_ECC_SERR = 109,
GAUDI2_EVENT_MME3_SBTE1_ECC_SERR = 110,
GAUDI2_EVENT_MME3_SBTE2_ECC_SERR = 111,
GAUDI2_EVENT_MME3_SBTE3_ECC_SERR = 112,
GAUDI2_EVENT_MME3_SBTE4_ECC_SERR = 113,
GAUDI2_EVENT_MME3_CTRL_ECC_SERR = 114,
GAUDI2_EVENT_MME3_WAP_ECC_SERR = 115,
GAUDI2_EVENT_MME0_SBTE0_ECC_DERR = 116,
GAUDI2_EVENT_MME0_SBTE1_ECC_DERR = 117,
Annotation
- Detected declarations: `enum gaudi2_async_event_id`.
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.