drivers/accel/habanalabs/include/gaudi2/gaudi2_coresight.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/gaudi2_coresight.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/gaudi2_coresight.h
Extension
.h
Size
27673 bytes
Lines
985
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef GAUDI2_CORESIGHT_H
#define GAUDI2_CORESIGHT_H

enum gaudi2_debug_stm_regs_index {
	GAUDI2_STM_FIRST = 0,
	GAUDI2_STM_DCORE0_TPC0_EML = GAUDI2_STM_FIRST,
	GAUDI2_STM_DCORE0_TPC1_EML,
	GAUDI2_STM_DCORE0_TPC2_EML,
	GAUDI2_STM_DCORE0_TPC3_EML,
	GAUDI2_STM_DCORE0_TPC4_EML,
	GAUDI2_STM_DCORE0_TPC5_EML,
	GAUDI2_STM_DCORE0_TPC6_EML,
	GAUDI2_STM_DCORE1_TPC0_EML,
	GAUDI2_STM_DCORE1_TPC1_EML,
	GAUDI2_STM_DCORE1_TPC2_EML,
	GAUDI2_STM_DCORE1_TPC3_EML,
	GAUDI2_STM_DCORE1_TPC4_EML,
	GAUDI2_STM_DCORE1_TPC5_EML,
	GAUDI2_STM_DCORE2_TPC0_EML,
	GAUDI2_STM_DCORE2_TPC1_EML,
	GAUDI2_STM_DCORE2_TPC2_EML,
	GAUDI2_STM_DCORE2_TPC3_EML,
	GAUDI2_STM_DCORE2_TPC4_EML,
	GAUDI2_STM_DCORE2_TPC5_EML,
	GAUDI2_STM_DCORE3_TPC0_EML,
	GAUDI2_STM_DCORE3_TPC1_EML,
	GAUDI2_STM_DCORE3_TPC2_EML,
	GAUDI2_STM_DCORE3_TPC3_EML,
	GAUDI2_STM_DCORE3_TPC4_EML,
	GAUDI2_STM_DCORE3_TPC5_EML,
	GAUDI2_STM_DCORE0_HMMU0_CS,
	GAUDI2_STM_DCORE0_HMMU1_CS,
	GAUDI2_STM_DCORE0_HMMU2_CS,
	GAUDI2_STM_DCORE0_HMMU3_CS,
	GAUDI2_STM_DCORE0_MME_CTRL,
	GAUDI2_STM_DCORE0_MME_SBTE0,
	GAUDI2_STM_DCORE0_MME_SBTE1,
	GAUDI2_STM_DCORE0_MME_SBTE2,
	GAUDI2_STM_DCORE0_MME_SBTE3,
	GAUDI2_STM_DCORE0_MME_SBTE4,
	GAUDI2_STM_DCORE0_MME_ACC,
	GAUDI2_STM_DCORE0_SM,
	GAUDI2_STM_DCORE0_EDMA0_CS,
	GAUDI2_STM_DCORE0_EDMA1_CS,
	GAUDI2_STM_DCORE0_VDEC0_CS,
	GAUDI2_STM_DCORE0_VDEC1_CS,
	GAUDI2_STM_DCORE1_HMMU0_CS,
	GAUDI2_STM_DCORE1_HMMU1_CS,
	GAUDI2_STM_DCORE1_HMMU2_CS,
	GAUDI2_STM_DCORE1_HMMU3_CS,
	GAUDI2_STM_DCORE1_MME_CTRL,
	GAUDI2_STM_DCORE1_MME_SBTE0,
	GAUDI2_STM_DCORE1_MME_SBTE1,
	GAUDI2_STM_DCORE1_MME_SBTE2,
	GAUDI2_STM_DCORE1_MME_SBTE3,
	GAUDI2_STM_DCORE1_MME_SBTE4,
	GAUDI2_STM_DCORE1_MME_ACC,
	GAUDI2_STM_DCORE1_SM,
	GAUDI2_STM_DCORE1_EDMA0_CS,
	GAUDI2_STM_DCORE1_EDMA1_CS,
	GAUDI2_STM_DCORE1_VDEC0_CS,
	GAUDI2_STM_DCORE1_VDEC1_CS,
	GAUDI2_STM_DCORE2_HMMU0_CS,
	GAUDI2_STM_DCORE2_HMMU1_CS,
	GAUDI2_STM_DCORE2_HMMU2_CS,
	GAUDI2_STM_DCORE2_HMMU3_CS,
	GAUDI2_STM_DCORE2_MME_CTRL,
	GAUDI2_STM_DCORE2_MME_SBTE0,
	GAUDI2_STM_DCORE2_MME_SBTE1,
	GAUDI2_STM_DCORE2_MME_SBTE2,
	GAUDI2_STM_DCORE2_MME_SBTE3,
	GAUDI2_STM_DCORE2_MME_SBTE4,
	GAUDI2_STM_DCORE2_MME_ACC,
	GAUDI2_STM_DCORE2_SM,
	GAUDI2_STM_DCORE2_EDMA0_CS,
	GAUDI2_STM_DCORE2_EDMA1_CS,
	GAUDI2_STM_DCORE2_VDEC0_CS,
	GAUDI2_STM_DCORE2_VDEC1_CS,
	GAUDI2_STM_DCORE3_HMMU0_CS,
	GAUDI2_STM_DCORE3_HMMU1_CS,
	GAUDI2_STM_DCORE3_HMMU2_CS,
	GAUDI2_STM_DCORE3_HMMU3_CS,
	GAUDI2_STM_DCORE3_MME_CTRL,
	GAUDI2_STM_DCORE3_MME_SBTE0,
	GAUDI2_STM_DCORE3_MME_SBTE1,
	GAUDI2_STM_DCORE3_MME_SBTE2,
	GAUDI2_STM_DCORE3_MME_SBTE3,
	GAUDI2_STM_DCORE3_MME_SBTE4,
	GAUDI2_STM_DCORE3_MME_ACC,
	GAUDI2_STM_DCORE3_SM,

Annotation

Implementation Notes