drivers/accel/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_masks.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_masks.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_masks.h
Extension
.h
Size
11062 bytes
Lines
191
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_CPU_CA53_CFG_MASKS_H_
#define ASIC_REG_CPU_CA53_CFG_MASKS_H_

/*
 *****************************************
 *   CPU_CA53_CFG (Prototype: CA53_CFG)
 *****************************************
 */

/* CPU_CA53_CFG_ARM_CFG */
#define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT                         0
#define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK                          0x3
#define CPU_CA53_CFG_ARM_CFG_END_SHIFT                               4
#define CPU_CA53_CFG_ARM_CFG_END_MASK                                0x30
#define CPU_CA53_CFG_ARM_CFG_TE_SHIFT                                8
#define CPU_CA53_CFG_ARM_CFG_TE_MASK                                 0x300
#define CPU_CA53_CFG_ARM_CFG_VINITHI_SHIFT                           12
#define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK                            0x3000

/* CPU_CA53_CFG_RST_ADDR_LSB */
#define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT                       0
#define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK                        0xFFFFFFFF

/* CPU_CA53_CFG_RST_ADDR_MSB */
#define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT                       0
#define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK                        0xFF

/* CPU_CA53_CFG_ARM_RST_CONTROL */
#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT               0
#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK                0x3
#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT                4
#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK                 0x30
#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT                  8
#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK                   0x100
#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT                12
#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK                 0x1000
#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT               16
#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK                0x10000
#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT                20
#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK                 0x300000

/* CPU_CA53_CFG_ARM_AFFINITY */
#define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_SHIFT                      0
#define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_MASK                       0xFF
#define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_SHIFT                      8
#define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_MASK                       0xFF00

/* CPU_CA53_CFG_ARM_DISABLE */
#define CPU_CA53_CFG_ARM_DISABLE_CP15S_SHIFT                         0
#define CPU_CA53_CFG_ARM_DISABLE_CP15S_MASK                          0x3
#define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_SHIFT                        4
#define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_MASK                         0x30
#define CPU_CA53_CFG_ARM_DISABLE_L2_RST_SHIFT                        8
#define CPU_CA53_CFG_ARM_DISABLE_L2_RST_MASK                         0x100
#define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_SHIFT                    9
#define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_MASK                     0x200

/* CPU_CA53_CFG_ARM_GIC_PERIPHBASE */
#define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_SHIFT             0
#define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_MASK              0x3FFFFF

/* CPU_CA53_CFG_ARM_GIC_IRQ_CFG */
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_SHIFT                      0
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_MASK                       0x3
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_SHIFT                      4
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_MASK                       0x30
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_SHIFT                      8
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_MASK                       0x300
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_SHIFT                      12
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_MASK                       0x3000
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_SHIFT                     16
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_MASK                      0x30000
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_SHIFT                     20
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_MASK                      0x300000
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_SHIFT                     24
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_MASK                      0x3000000
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_SHIFT                    31
#define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_MASK                     0x80000000

/* CPU_CA53_CFG_ARM_PWR_MNG */
#define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_SHIFT                   0
#define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_MASK                    0x1
#define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_SHIFT                        1
#define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_MASK                         0x2
#define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_SHIFT                    2
#define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_MASK                     0x4
#define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_SHIFT                       3
#define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_MASK                        0x8
#define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_SHIFT                      4
#define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_MASK                       0x30

Annotation

Implementation Notes