drivers/accel/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_regs.h

File Facts

System: Linux kernel
Corpus path: drivers/accel/habanalabs/include/goya/asic_reg/cpu_ca53_cfg_regs.h
Extension: .h
Size: 2020 bytes
Lines: 61
Domain: Driver Families
Bucket: drivers/accel
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_CPU_CA53_CFG_REGS_H_
#define ASIC_REG_CPU_CA53_CFG_REGS_H_

/*
 *****************************************
 *   CPU_CA53_CFG (Prototype: CA53_CFG)
 *****************************************
 */

#define mmCPU_CA53_CFG_ARM_CFG                                       0x441100

#define mmCPU_CA53_CFG_RST_ADDR_LSB_0                                0x441104

#define mmCPU_CA53_CFG_RST_ADDR_LSB_1                                0x441108

#define mmCPU_CA53_CFG_RST_ADDR_MSB_0                                0x441114

#define mmCPU_CA53_CFG_RST_ADDR_MSB_1                                0x441118

#define mmCPU_CA53_CFG_ARM_RST_CONTROL                               0x441124

#define mmCPU_CA53_CFG_ARM_AFFINITY                                  0x441128

#define mmCPU_CA53_CFG_ARM_DISABLE                                   0x44112C

#define mmCPU_CA53_CFG_ARM_GIC_PERIPHBASE                            0x441130

#define mmCPU_CA53_CFG_ARM_GIC_IRQ_CFG                               0x441134

#define mmCPU_CA53_CFG_ARM_PWR_MNG                                   0x441138

#define mmCPU_CA53_CFG_ARB_DBG_ROM_ADDR                              0x44113C

#define mmCPU_CA53_CFG_ARM_DBG_MODES                                 0x441140

#define mmCPU_CA53_CFG_ARM_PWR_STAT_0                                0x441200

#define mmCPU_CA53_CFG_ARM_PWR_STAT_1                                0x441204

#define mmCPU_CA53_CFG_ARM_DBG_STATUS                                0x441208

#define mmCPU_CA53_CFG_ARM_MEM_ATTR                                  0x44120C

#define mmCPU_CA53_CFG_ARM_PMU_0                                     0x441210

#define mmCPU_CA53_CFG_ARM_PMU_1                                     0x441214

#endif /* ASIC_REG_CPU_CA53_CFG_REGS_H_ */

Annotation

Atlas domain: Driver Families / drivers/accel.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.