drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_0_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_0_regs.h

Extension

.h

Size

7848 bytes

Lines

209

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DMA_CH_0_REGS_H_
#define ASIC_REG_DMA_CH_0_REGS_H_

/*
 *****************************************
 *   DMA_CH_0 (Prototype: DMA_CH)
 *****************************************
 */

#define mmDMA_CH_0_CFG0                                              0x401000

#define mmDMA_CH_0_CFG1                                              0x401004

#define mmDMA_CH_0_ERRMSG_ADDR_LO                                    0x401008

#define mmDMA_CH_0_ERRMSG_ADDR_HI                                    0x40100C

#define mmDMA_CH_0_ERRMSG_WDATA                                      0x401010

#define mmDMA_CH_0_RD_COMP_ADDR_LO                                   0x401014

#define mmDMA_CH_0_RD_COMP_ADDR_HI                                   0x401018

#define mmDMA_CH_0_RD_COMP_WDATA                                     0x40101C

#define mmDMA_CH_0_WR_COMP_ADDR_LO                                   0x401020

#define mmDMA_CH_0_WR_COMP_ADDR_HI                                   0x401024

#define mmDMA_CH_0_WR_COMP_WDATA                                     0x401028

#define mmDMA_CH_0_LDMA_SRC_ADDR_LO                                  0x40102C

#define mmDMA_CH_0_LDMA_SRC_ADDR_HI                                  0x401030

#define mmDMA_CH_0_LDMA_DST_ADDR_LO                                  0x401034

#define mmDMA_CH_0_LDMA_DST_ADDR_HI                                  0x401038

#define mmDMA_CH_0_LDMA_TSIZE                                        0x40103C

#define mmDMA_CH_0_COMIT_TRANSFER                                    0x401040

#define mmDMA_CH_0_STS0                                              0x401044

#define mmDMA_CH_0_STS1                                              0x401048

#define mmDMA_CH_0_STS2                                              0x40104C

#define mmDMA_CH_0_STS3                                              0x401050

#define mmDMA_CH_0_STS4                                              0x401054

#define mmDMA_CH_0_SRC_ADDR_LO_STS                                   0x401058

#define mmDMA_CH_0_SRC_ADDR_HI_STS                                   0x40105C

#define mmDMA_CH_0_SRC_TSIZE_STS                                     0x401060

#define mmDMA_CH_0_DST_ADDR_LO_STS                                   0x401064

#define mmDMA_CH_0_DST_ADDR_HI_STS                                   0x401068

#define mmDMA_CH_0_DST_TSIZE_STS                                     0x40106C

#define mmDMA_CH_0_RD_RATE_LIM_EN                                    0x401070

#define mmDMA_CH_0_RD_RATE_LIM_RST_TOKEN                             0x401074

#define mmDMA_CH_0_RD_RATE_LIM_SAT                                   0x401078

#define mmDMA_CH_0_RD_RATE_LIM_TOUT                                  0x40107C

#define mmDMA_CH_0_WR_RATE_LIM_EN                                    0x401080

#define mmDMA_CH_0_WR_RATE_LIM_RST_TOKEN                             0x401084

#define mmDMA_CH_0_WR_RATE_LIM_SAT                                   0x401088

#define mmDMA_CH_0_WR_RATE_LIM_TOUT                                  0x40108C

#define mmDMA_CH_0_CFG2                                              0x401090

#define mmDMA_CH_0_TDMA_CTL                                          0x401100

#define mmDMA_CH_0_TDMA_SRC_BASE_ADDR_LO                             0x401104

#define mmDMA_CH_0_TDMA_SRC_BASE_ADDR_HI                             0x401108

#define mmDMA_CH_0_TDMA_SRC_ROI_BASE_0                               0x40110C

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.