drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_1_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/dma_ch_1_regs.h

Extension

.h

Size

7848 bytes

Lines

209

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DMA_CH_1_REGS_H_
#define ASIC_REG_DMA_CH_1_REGS_H_

/*
 *****************************************
 *   DMA_CH_1 (Prototype: DMA_CH)
 *****************************************
 */

#define mmDMA_CH_1_CFG0                                              0x409000

#define mmDMA_CH_1_CFG1                                              0x409004

#define mmDMA_CH_1_ERRMSG_ADDR_LO                                    0x409008

#define mmDMA_CH_1_ERRMSG_ADDR_HI                                    0x40900C

#define mmDMA_CH_1_ERRMSG_WDATA                                      0x409010

#define mmDMA_CH_1_RD_COMP_ADDR_LO                                   0x409014

#define mmDMA_CH_1_RD_COMP_ADDR_HI                                   0x409018

#define mmDMA_CH_1_RD_COMP_WDATA                                     0x40901C

#define mmDMA_CH_1_WR_COMP_ADDR_LO                                   0x409020

#define mmDMA_CH_1_WR_COMP_ADDR_HI                                   0x409024

#define mmDMA_CH_1_WR_COMP_WDATA                                     0x409028

#define mmDMA_CH_1_LDMA_SRC_ADDR_LO                                  0x40902C

#define mmDMA_CH_1_LDMA_SRC_ADDR_HI                                  0x409030

#define mmDMA_CH_1_LDMA_DST_ADDR_LO                                  0x409034

#define mmDMA_CH_1_LDMA_DST_ADDR_HI                                  0x409038

#define mmDMA_CH_1_LDMA_TSIZE                                        0x40903C

#define mmDMA_CH_1_COMIT_TRANSFER                                    0x409040

#define mmDMA_CH_1_STS0                                              0x409044

#define mmDMA_CH_1_STS1                                              0x409048

#define mmDMA_CH_1_STS2                                              0x40904C

#define mmDMA_CH_1_STS3                                              0x409050

#define mmDMA_CH_1_STS4                                              0x409054

#define mmDMA_CH_1_SRC_ADDR_LO_STS                                   0x409058

#define mmDMA_CH_1_SRC_ADDR_HI_STS                                   0x40905C

#define mmDMA_CH_1_SRC_TSIZE_STS                                     0x409060

#define mmDMA_CH_1_DST_ADDR_LO_STS                                   0x409064

#define mmDMA_CH_1_DST_ADDR_HI_STS                                   0x409068

#define mmDMA_CH_1_DST_TSIZE_STS                                     0x40906C

#define mmDMA_CH_1_RD_RATE_LIM_EN                                    0x409070

#define mmDMA_CH_1_RD_RATE_LIM_RST_TOKEN                             0x409074

#define mmDMA_CH_1_RD_RATE_LIM_SAT                                   0x409078

#define mmDMA_CH_1_RD_RATE_LIM_TOUT                                  0x40907C

#define mmDMA_CH_1_WR_RATE_LIM_EN                                    0x409080

#define mmDMA_CH_1_WR_RATE_LIM_RST_TOKEN                             0x409084

#define mmDMA_CH_1_WR_RATE_LIM_SAT                                   0x409088

#define mmDMA_CH_1_WR_RATE_LIM_TOUT                                  0x40908C

#define mmDMA_CH_1_CFG2                                              0x409090

#define mmDMA_CH_1_TDMA_CTL                                          0x409100

#define mmDMA_CH_1_TDMA_SRC_BASE_ADDR_LO                             0x409104

#define mmDMA_CH_1_TDMA_SRC_BASE_ADDR_HI                             0x409108

#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_0                               0x40910C

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.