drivers/accel/habanalabs/include/goya/asic_reg/dma_macro_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/dma_macro_regs.h

Extension

.h

Size

6749 bytes

Lines

181

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DMA_MACRO_REGS_H_
#define ASIC_REG_DMA_MACRO_REGS_H_

/*
 *****************************************
 *   DMA_MACRO (Prototype: DMA_MACRO)
 *****************************************
 */

#define mmDMA_MACRO_LBW_RANGE_HIT_BLOCK                              0x4B0000

#define mmDMA_MACRO_LBW_RANGE_MASK_0                                 0x4B0004

#define mmDMA_MACRO_LBW_RANGE_MASK_1                                 0x4B0008

#define mmDMA_MACRO_LBW_RANGE_MASK_2                                 0x4B000C

#define mmDMA_MACRO_LBW_RANGE_MASK_3                                 0x4B0010

#define mmDMA_MACRO_LBW_RANGE_MASK_4                                 0x4B0014

#define mmDMA_MACRO_LBW_RANGE_MASK_5                                 0x4B0018

#define mmDMA_MACRO_LBW_RANGE_MASK_6                                 0x4B001C

#define mmDMA_MACRO_LBW_RANGE_MASK_7                                 0x4B0020

#define mmDMA_MACRO_LBW_RANGE_MASK_8                                 0x4B0024

#define mmDMA_MACRO_LBW_RANGE_MASK_9                                 0x4B0028

#define mmDMA_MACRO_LBW_RANGE_MASK_10                                0x4B002C

#define mmDMA_MACRO_LBW_RANGE_MASK_11                                0x4B0030

#define mmDMA_MACRO_LBW_RANGE_MASK_12                                0x4B0034

#define mmDMA_MACRO_LBW_RANGE_MASK_13                                0x4B0038

#define mmDMA_MACRO_LBW_RANGE_MASK_14                                0x4B003C

#define mmDMA_MACRO_LBW_RANGE_MASK_15                                0x4B0040

#define mmDMA_MACRO_LBW_RANGE_BASE_0                                 0x4B0044

#define mmDMA_MACRO_LBW_RANGE_BASE_1                                 0x4B0048

#define mmDMA_MACRO_LBW_RANGE_BASE_2                                 0x4B004C

#define mmDMA_MACRO_LBW_RANGE_BASE_3                                 0x4B0050

#define mmDMA_MACRO_LBW_RANGE_BASE_4                                 0x4B0054

#define mmDMA_MACRO_LBW_RANGE_BASE_5                                 0x4B0058

#define mmDMA_MACRO_LBW_RANGE_BASE_6                                 0x4B005C

#define mmDMA_MACRO_LBW_RANGE_BASE_7                                 0x4B0060

#define mmDMA_MACRO_LBW_RANGE_BASE_8                                 0x4B0064

#define mmDMA_MACRO_LBW_RANGE_BASE_9                                 0x4B0068

#define mmDMA_MACRO_LBW_RANGE_BASE_10                                0x4B006C

#define mmDMA_MACRO_LBW_RANGE_BASE_11                                0x4B0070

#define mmDMA_MACRO_LBW_RANGE_BASE_12                                0x4B0074

#define mmDMA_MACRO_LBW_RANGE_BASE_13                                0x4B0078

#define mmDMA_MACRO_LBW_RANGE_BASE_14                                0x4B007C

#define mmDMA_MACRO_LBW_RANGE_BASE_15                                0x4B0080

#define mmDMA_MACRO_HBW_RANGE_HIT_BLOCK                              0x4B0084

#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_0                           0x4B00A8

#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_1                           0x4B00AC

#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_2                           0x4B00B0

#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_3                           0x4B00B4

#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_4                           0x4B00B8

#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_5                           0x4B00BC

#define mmDMA_MACRO_HBW_RANGE_MASK_49_32_6                           0x4B00C0

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.