drivers/accel/habanalabs/include/goya/asic_reg/dma_nrtr_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/dma_nrtr_regs.h

Extension

.h

Size

8560 bytes

Lines

227

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DMA_NRTR_REGS_H_
#define ASIC_REG_DMA_NRTR_REGS_H_

/*
 *****************************************
 *   DMA_NRTR (Prototype: IF_NRTR)
 *****************************************
 */

#define mmDMA_NRTR_HBW_MAX_CRED                                      0x1C0100

#define mmDMA_NRTR_LBW_MAX_CRED                                      0x1C0120

#define mmDMA_NRTR_DBG_E_ARB                                         0x1C0300

#define mmDMA_NRTR_DBG_W_ARB                                         0x1C0304

#define mmDMA_NRTR_DBG_N_ARB                                         0x1C0308

#define mmDMA_NRTR_DBG_S_ARB                                         0x1C030C

#define mmDMA_NRTR_DBG_L_ARB                                         0x1C0310

#define mmDMA_NRTR_DBG_E_ARB_MAX                                     0x1C0320

#define mmDMA_NRTR_DBG_W_ARB_MAX                                     0x1C0324

#define mmDMA_NRTR_DBG_N_ARB_MAX                                     0x1C0328

#define mmDMA_NRTR_DBG_S_ARB_MAX                                     0x1C032C

#define mmDMA_NRTR_DBG_L_ARB_MAX                                     0x1C0330

#define mmDMA_NRTR_SPLIT_COEF_0                                      0x1C0400

#define mmDMA_NRTR_SPLIT_COEF_1                                      0x1C0404

#define mmDMA_NRTR_SPLIT_COEF_2                                      0x1C0408

#define mmDMA_NRTR_SPLIT_COEF_3                                      0x1C040C

#define mmDMA_NRTR_SPLIT_COEF_4                                      0x1C0410

#define mmDMA_NRTR_SPLIT_COEF_5                                      0x1C0414

#define mmDMA_NRTR_SPLIT_COEF_6                                      0x1C0418

#define mmDMA_NRTR_SPLIT_COEF_7                                      0x1C041C

#define mmDMA_NRTR_SPLIT_COEF_8                                      0x1C0420

#define mmDMA_NRTR_SPLIT_COEF_9                                      0x1C0424

#define mmDMA_NRTR_SPLIT_CFG                                         0x1C0440

#define mmDMA_NRTR_SPLIT_RD_SAT                                      0x1C0444

#define mmDMA_NRTR_SPLIT_RD_RST_TOKEN                                0x1C0448

#define mmDMA_NRTR_SPLIT_RD_TIMEOUT_0                                0x1C044C

#define mmDMA_NRTR_SPLIT_RD_TIMEOUT_1                                0x1C0450

#define mmDMA_NRTR_SPLIT_WR_SAT                                      0x1C0454

#define mmDMA_NRTR_WPLIT_WR_TST_TOLEN                                0x1C0458

#define mmDMA_NRTR_SPLIT_WR_TIMEOUT_0                                0x1C045C

#define mmDMA_NRTR_SPLIT_WR_TIMEOUT_1                                0x1C0460

#define mmDMA_NRTR_HBW_RANGE_HIT                                     0x1C0470

#define mmDMA_NRTR_HBW_RANGE_MASK_L_0                                0x1C0480

#define mmDMA_NRTR_HBW_RANGE_MASK_L_1                                0x1C0484

#define mmDMA_NRTR_HBW_RANGE_MASK_L_2                                0x1C0488

#define mmDMA_NRTR_HBW_RANGE_MASK_L_3                                0x1C048C

#define mmDMA_NRTR_HBW_RANGE_MASK_L_4                                0x1C0490

#define mmDMA_NRTR_HBW_RANGE_MASK_L_5                                0x1C0494

#define mmDMA_NRTR_HBW_RANGE_MASK_L_6                                0x1C0498

#define mmDMA_NRTR_HBW_RANGE_MASK_L_7                                0x1C049C

#define mmDMA_NRTR_HBW_RANGE_MASK_H_0                                0x1C04A0

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.