drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_2_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_2_regs.h

Extension

.h

Size

6661 bytes

Lines

179

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DMA_QM_2_REGS_H_
#define ASIC_REG_DMA_QM_2_REGS_H_

/*
 *****************************************
 *   DMA_QM_2 (Prototype: QMAN)
 *****************************************
 */

#define mmDMA_QM_2_GLBL_CFG0                                         0x410000

#define mmDMA_QM_2_GLBL_CFG1                                         0x410004

#define mmDMA_QM_2_GLBL_PROT                                         0x410008

#define mmDMA_QM_2_GLBL_ERR_CFG                                      0x41000C

#define mmDMA_QM_2_GLBL_ERR_ADDR_LO                                  0x410010

#define mmDMA_QM_2_GLBL_ERR_ADDR_HI                                  0x410014

#define mmDMA_QM_2_GLBL_ERR_WDATA                                    0x410018

#define mmDMA_QM_2_GLBL_SECURE_PROPS                                 0x41001C

#define mmDMA_QM_2_GLBL_NON_SECURE_PROPS                             0x410020

#define mmDMA_QM_2_GLBL_STS0                                         0x410024

#define mmDMA_QM_2_GLBL_STS1                                         0x410028

#define mmDMA_QM_2_PQ_BASE_LO                                        0x410060

#define mmDMA_QM_2_PQ_BASE_HI                                        0x410064

#define mmDMA_QM_2_PQ_SIZE                                           0x410068

#define mmDMA_QM_2_PQ_PI                                             0x41006C

#define mmDMA_QM_2_PQ_CI                                             0x410070

#define mmDMA_QM_2_PQ_CFG0                                           0x410074

#define mmDMA_QM_2_PQ_CFG1                                           0x410078

#define mmDMA_QM_2_PQ_ARUSER                                         0x41007C

#define mmDMA_QM_2_PQ_PUSH0                                          0x410080

#define mmDMA_QM_2_PQ_PUSH1                                          0x410084

#define mmDMA_QM_2_PQ_PUSH2                                          0x410088

#define mmDMA_QM_2_PQ_PUSH3                                          0x41008C

#define mmDMA_QM_2_PQ_STS0                                           0x410090

#define mmDMA_QM_2_PQ_STS1                                           0x410094

#define mmDMA_QM_2_PQ_RD_RATE_LIM_EN                                 0x4100A0

#define mmDMA_QM_2_PQ_RD_RATE_LIM_RST_TOKEN                          0x4100A4

#define mmDMA_QM_2_PQ_RD_RATE_LIM_SAT                                0x4100A8

#define mmDMA_QM_2_PQ_RD_RATE_LIM_TOUT                               0x4100AC

#define mmDMA_QM_2_CQ_CFG0                                           0x4100B0

#define mmDMA_QM_2_CQ_CFG1                                           0x4100B4

#define mmDMA_QM_2_CQ_ARUSER                                         0x4100B8

#define mmDMA_QM_2_CQ_PTR_LO                                         0x4100C0

#define mmDMA_QM_2_CQ_PTR_HI                                         0x4100C4

#define mmDMA_QM_2_CQ_TSIZE                                          0x4100C8

#define mmDMA_QM_2_CQ_CTL                                            0x4100CC

#define mmDMA_QM_2_CQ_PTR_LO_STS                                     0x4100D4

#define mmDMA_QM_2_CQ_PTR_HI_STS                                     0x4100D8

#define mmDMA_QM_2_CQ_TSIZE_STS                                      0x4100DC

#define mmDMA_QM_2_CQ_CTL_STS                                        0x4100E0

#define mmDMA_QM_2_CQ_STS0                                           0x4100E4

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.