drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_3_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/dma_qm_3_regs.h

Extension

.h

Size

6661 bytes

Lines

179

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DMA_QM_3_REGS_H_
#define ASIC_REG_DMA_QM_3_REGS_H_

/*
 *****************************************
 *   DMA_QM_3 (Prototype: QMAN)
 *****************************************
 */

#define mmDMA_QM_3_GLBL_CFG0                                         0x418000

#define mmDMA_QM_3_GLBL_CFG1                                         0x418004

#define mmDMA_QM_3_GLBL_PROT                                         0x418008

#define mmDMA_QM_3_GLBL_ERR_CFG                                      0x41800C

#define mmDMA_QM_3_GLBL_ERR_ADDR_LO                                  0x418010

#define mmDMA_QM_3_GLBL_ERR_ADDR_HI                                  0x418014

#define mmDMA_QM_3_GLBL_ERR_WDATA                                    0x418018

#define mmDMA_QM_3_GLBL_SECURE_PROPS                                 0x41801C

#define mmDMA_QM_3_GLBL_NON_SECURE_PROPS                             0x418020

#define mmDMA_QM_3_GLBL_STS0                                         0x418024

#define mmDMA_QM_3_GLBL_STS1                                         0x418028

#define mmDMA_QM_3_PQ_BASE_LO                                        0x418060

#define mmDMA_QM_3_PQ_BASE_HI                                        0x418064

#define mmDMA_QM_3_PQ_SIZE                                           0x418068

#define mmDMA_QM_3_PQ_PI                                             0x41806C

#define mmDMA_QM_3_PQ_CI                                             0x418070

#define mmDMA_QM_3_PQ_CFG0                                           0x418074

#define mmDMA_QM_3_PQ_CFG1                                           0x418078

#define mmDMA_QM_3_PQ_ARUSER                                         0x41807C

#define mmDMA_QM_3_PQ_PUSH0                                          0x418080

#define mmDMA_QM_3_PQ_PUSH1                                          0x418084

#define mmDMA_QM_3_PQ_PUSH2                                          0x418088

#define mmDMA_QM_3_PQ_PUSH3                                          0x41808C

#define mmDMA_QM_3_PQ_STS0                                           0x418090

#define mmDMA_QM_3_PQ_STS1                                           0x418094

#define mmDMA_QM_3_PQ_RD_RATE_LIM_EN                                 0x4180A0

#define mmDMA_QM_3_PQ_RD_RATE_LIM_RST_TOKEN                          0x4180A4

#define mmDMA_QM_3_PQ_RD_RATE_LIM_SAT                                0x4180A8

#define mmDMA_QM_3_PQ_RD_RATE_LIM_TOUT                               0x4180AC

#define mmDMA_QM_3_CQ_CFG0                                           0x4180B0

#define mmDMA_QM_3_CQ_CFG1                                           0x4180B4

#define mmDMA_QM_3_CQ_ARUSER                                         0x4180B8

#define mmDMA_QM_3_CQ_PTR_LO                                         0x4180C0

#define mmDMA_QM_3_CQ_PTR_HI                                         0x4180C4

#define mmDMA_QM_3_CQ_TSIZE                                          0x4180C8

#define mmDMA_QM_3_CQ_CTL                                            0x4180CC

#define mmDMA_QM_3_CQ_PTR_LO_STS                                     0x4180D4

#define mmDMA_QM_3_CQ_PTR_HI_STS                                     0x4180D8

#define mmDMA_QM_3_CQ_TSIZE_STS                                      0x4180DC

#define mmDMA_QM_3_CQ_CTL_STS                                        0x4180E0

#define mmDMA_QM_3_CQ_STS0                                           0x4180E4

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.