drivers/accel/habanalabs/include/goya/asic_reg/goya_blocks.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/goya/asic_reg/goya_blocks.h

File Facts

System: Linux kernel
Corpus path: drivers/accel/habanalabs/include/goya/asic_reg/goya_blocks.h
Extension: .h
Size: 82732 bytes
Lines: 1373
Domain: Driver Families
Bucket: drivers/accel
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef GOYA_BLOCKS_H_
#define GOYA_BLOCKS_H_

#define mmPCI_NRTR_BASE                            0x7FFC000000ull
#define PCI_NRTR_MAX_OFFSET                        0x608
#define PCI_NRTR_SECTION                           0x4000
#define mmPCI_RD_REGULATOR_BASE                    0x7FFC004000ull
#define PCI_RD_REGULATOR_MAX_OFFSET                0x74
#define PCI_RD_REGULATOR_SECTION                   0x1000
#define mmPCI_WR_REGULATOR_BASE                    0x7FFC005000ull
#define PCI_WR_REGULATOR_MAX_OFFSET                0x74
#define PCI_WR_REGULATOR_SECTION                   0x3B000
#define mmMME1_RTR_BASE                            0x7FFC040000ull
#define MME1_RTR_MAX_OFFSET                        0x608
#define MME1_RTR_SECTION                           0x4000
#define mmMME1_RD_REGULATOR_BASE                   0x7FFC044000ull
#define MME1_RD_REGULATOR_MAX_OFFSET               0x74
#define MME1_RD_REGULATOR_SECTION                  0x1000
#define mmMME1_WR_REGULATOR_BASE                   0x7FFC045000ull
#define MME1_WR_REGULATOR_MAX_OFFSET               0x74
#define MME1_WR_REGULATOR_SECTION                  0x3B000
#define mmMME2_RTR_BASE                            0x7FFC080000ull
#define MME2_RTR_MAX_OFFSET                        0x608
#define MME2_RTR_SECTION                           0x4000
#define mmMME2_RD_REGULATOR_BASE                   0x7FFC084000ull
#define MME2_RD_REGULATOR_MAX_OFFSET               0x74
#define MME2_RD_REGULATOR_SECTION                  0x1000
#define mmMME2_WR_REGULATOR_BASE                   0x7FFC085000ull
#define MME2_WR_REGULATOR_MAX_OFFSET               0x74
#define MME2_WR_REGULATOR_SECTION                  0x3B000
#define mmMME3_RTR_BASE                            0x7FFC0C0000ull
#define MME3_RTR_MAX_OFFSET                        0x608
#define MME3_RTR_SECTION                           0x4000
#define mmMME3_RD_REGULATOR_BASE                   0x7FFC0C4000ull
#define MME3_RD_REGULATOR_MAX_OFFSET               0x74
#define MME3_RD_REGULATOR_SECTION                  0x1000
#define mmMME3_WR_REGULATOR_BASE                   0x7FFC0C5000ull
#define MME3_WR_REGULATOR_MAX_OFFSET               0x74
#define MME3_WR_REGULATOR_SECTION                  0xB000
#define mmMME_BASE                                 0x7FFC0D0000ull
#define MME_MAX_OFFSET                             0xBB0
#define MME_SECTION                                0x8000
#define mmMME_QM_BASE                              0x7FFC0D8000ull
#define MME_QM_MAX_OFFSET                          0x310
#define MME_QM_SECTION                             0x1000
#define mmMME_CMDQ_BASE                            0x7FFC0D9000ull
#define MME_CMDQ_MAX_OFFSET                        0x310
#define MME_CMDQ_SECTION                           0x1000
#define mmACC_MS_ECC_MEM_0_BASE                    0x7FFC0DA000ull
#define ACC_MS_ECC_MEM_0_MAX_OFFSET                0x0
#define ACC_MS_ECC_MEM_0_SECTION                   0x1000
#define mmACC_MS_ECC_MEM_1_BASE                    0x7FFC0DB000ull
#define ACC_MS_ECC_MEM_1_MAX_OFFSET                0x0
#define ACC_MS_ECC_MEM_1_SECTION                   0x1000
#define mmACC_MS_ECC_MEM_2_BASE                    0x7FFC0DC000ull
#define ACC_MS_ECC_MEM_2_MAX_OFFSET                0x0
#define ACC_MS_ECC_MEM_2_SECTION                   0x1000
#define mmACC_MS_ECC_MEM_3_BASE                    0x7FFC0DD000ull
#define ACC_MS_ECC_MEM_3_MAX_OFFSET                0x0
#define ACC_MS_ECC_MEM_3_SECTION                   0x1000
#define mmSBA_ECC_MEM_BASE                         0x7FFC0DE000ull
#define SBA_ECC_MEM_MAX_OFFSET                     0x0
#define SBA_ECC_MEM_SECTION                        0x1000
#define mmSBB_ECC_MEM_BASE                         0x7FFC0DF000ull
#define SBB_ECC_MEM_MAX_OFFSET                     0x0
#define SBB_ECC_MEM_SECTION                        0x21000
#define mmMME4_RTR_BASE                            0x7FFC100000ull
#define MME4_RTR_MAX_OFFSET                        0x608
#define MME4_RTR_SECTION                           0x4000
#define mmMME4_RD_REGULATOR_BASE                   0x7FFC104000ull
#define MME4_RD_REGULATOR_MAX_OFFSET               0x74
#define MME4_RD_REGULATOR_SECTION                  0x1000
#define mmMME4_WR_REGULATOR_BASE                   0x7FFC105000ull
#define MME4_WR_REGULATOR_MAX_OFFSET               0x74
#define MME4_WR_REGULATOR_SECTION                  0xB000
#define mmSYNC_MNGR_BASE                           0x7FFC110000ull
#define SYNC_MNGR_MAX_OFFSET                       0x4400
#define SYNC_MNGR_SECTION                          0x30000
#define mmMME5_RTR_BASE                            0x7FFC140000ull
#define MME5_RTR_MAX_OFFSET                        0x608
#define MME5_RTR_SECTION                           0x4000
#define mmMME5_RD_REGULATOR_BASE                   0x7FFC144000ull
#define MME5_RD_REGULATOR_MAX_OFFSET               0x74
#define MME5_RD_REGULATOR_SECTION                  0x1000
#define mmMME5_WR_REGULATOR_BASE                   0x7FFC145000ull
#define MME5_WR_REGULATOR_MAX_OFFSET               0x74
#define MME5_WR_REGULATOR_SECTION                  0x3B000
#define mmMME6_RTR_BASE                            0x7FFC180000ull
#define MME6_RTR_MAX_OFFSET                        0x608
#define MME6_RTR_SECTION                           0x4000

Annotation

Atlas domain: Driver Families / drivers/accel.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.