drivers/accel/habanalabs/include/goya/asic_reg/goya_masks.h
Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/goya/asic_reg/goya_masks.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/habanalabs/include/goya/asic_reg/goya_masks.h- Extension
.h- Size
- 10138 bytes
- Lines
- 268
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
goya_regs.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef ASIC_REG_GOYA_MASKS_H_
#define ASIC_REG_GOYA_MASKS_H_
#include "goya_regs.h"
/* Useful masks for bits in various registers */
#define QMAN_DMA_ENABLE (\
(1 << DMA_QM_0_GLBL_CFG0_PQF_EN_SHIFT) | \
(1 << DMA_QM_0_GLBL_CFG0_CQF_EN_SHIFT) | \
(1 << DMA_QM_0_GLBL_CFG0_CP_EN_SHIFT) | \
(1 << DMA_QM_0_GLBL_CFG0_DMA_EN_SHIFT))
#define QMAN_DMA_FULLY_TRUSTED (\
(1 << DMA_QM_0_GLBL_PROT_PQF_PROT_SHIFT) | \
(1 << DMA_QM_0_GLBL_PROT_CQF_PROT_SHIFT) | \
(1 << DMA_QM_0_GLBL_PROT_CP_PROT_SHIFT) | \
(1 << DMA_QM_0_GLBL_PROT_DMA_PROT_SHIFT) | \
(1 << DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \
(1 << DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \
(1 << DMA_QM_0_GLBL_PROT_CP_ERR_PROT_SHIFT) | \
(1 << DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_SHIFT))
#define QMAN_DMA_PARTLY_TRUSTED (\
(1 << DMA_QM_0_GLBL_PROT_PQF_PROT_SHIFT) | \
(1 << DMA_QM_0_GLBL_PROT_CQF_PROT_SHIFT) | \
(1 << DMA_QM_0_GLBL_PROT_CP_PROT_SHIFT) | \
(1 << DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \
(1 << DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \
(1 << DMA_QM_0_GLBL_PROT_CP_ERR_PROT_SHIFT) | \
(1 << DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_SHIFT))
#define QMAN_DMA_STOP (\
(1 << DMA_QM_0_GLBL_CFG1_PQF_STOP_SHIFT) | \
(1 << DMA_QM_0_GLBL_CFG1_CQF_STOP_SHIFT) | \
(1 << DMA_QM_0_GLBL_CFG1_CP_STOP_SHIFT) | \
(1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT))
#define QMAN_DMA_IS_STOPPED (\
(1 << DMA_QM_0_GLBL_STS0_PQF_IS_STOP_SHIFT) | \
(1 << DMA_QM_0_GLBL_STS0_CQF_IS_STOP_SHIFT) | \
(1 << DMA_QM_0_GLBL_STS0_CP_IS_STOP_SHIFT) | \
(1 << DMA_QM_0_GLBL_STS0_DMA_IS_STOP_SHIFT))
#define QMAN_DMA_ERR_MSG_EN (\
(1 << DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
(1 << DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
(1 << DMA_QM_0_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \
(1 << DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \
(1 << DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
(1 << DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
(1 << DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT))
#define QMAN_MME_ENABLE (\
(1 << MME_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
(1 << MME_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
(1 << MME_QM_GLBL_CFG0_CP_EN_SHIFT))
#define CMDQ_MME_ENABLE (\
(1 << MME_CMDQ_GLBL_CFG0_CQF_EN_SHIFT) | \
(1 << MME_CMDQ_GLBL_CFG0_CP_EN_SHIFT))
#define QMAN_MME_STOP (\
(1 << MME_QM_GLBL_CFG1_PQF_STOP_SHIFT) | \
(1 << MME_QM_GLBL_CFG1_CQF_STOP_SHIFT) | \
(1 << MME_QM_GLBL_CFG1_CP_STOP_SHIFT))
#define CMDQ_MME_STOP (\
(1 << MME_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT) | \
(1 << MME_CMDQ_GLBL_CFG1_CP_STOP_SHIFT))
#define QMAN_MME_ERR_MSG_EN (\
(1 << MME_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
(1 << MME_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
(1 << MME_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \
(1 << MME_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \
(1 << MME_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
(1 << MME_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
(1 << MME_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \
(1 << MME_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT))
#define CMDQ_MME_ERR_MSG_EN (\
(1 << MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
(1 << MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
(1 << MME_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \
(1 << MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \
(1 << MME_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
(1 << MME_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
(1 << MME_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \
(1 << MME_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT))
Annotation
- Immediate include surface: `goya_regs.h`.
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.