drivers/accel/habanalabs/include/goya/asic_reg/goya_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/goya_regs.h

Extension

.h

Size

3647 bytes

Lines

123

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

• goya_blocks.h
• stlb_regs.h
• mmu_regs.h
• pcie_aux_regs.h
• pcie_wrap_regs.h
• psoc_global_conf_regs.h
• psoc_spi_regs.h
• psoc_mme_pll_regs.h
• psoc_pci_pll_regs.h
• psoc_emmc_pll_regs.h
• psoc_timestamp_regs.h
• cpu_if_regs.h
• cpu_ca53_cfg_regs.h
• cpu_pll_regs.h
• ic_pll_regs.h
• mc_pll_regs.h
• tpc_pll_regs.h
• dma_qm_0_regs.h
• dma_qm_1_regs.h
• dma_qm_2_regs.h
• dma_qm_3_regs.h
• dma_qm_4_regs.h
• dma_ch_0_regs.h
• dma_ch_1_regs.h
• dma_ch_2_regs.h
• dma_ch_3_regs.h
• dma_ch_4_regs.h
• dma_macro_regs.h
• dma_nrtr_regs.h
• pci_nrtr_regs.h
• sram_y0_x0_rtr_regs.h
• sram_y0_x1_rtr_regs.h

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_GOYA_REGS_H_
#define ASIC_REG_GOYA_REGS_H_

#include "goya_blocks.h"
#include "stlb_regs.h"
#include "mmu_regs.h"
#include "pcie_aux_regs.h"
#include "pcie_wrap_regs.h"
#include "psoc_global_conf_regs.h"
#include "psoc_spi_regs.h"
#include "psoc_mme_pll_regs.h"
#include "psoc_pci_pll_regs.h"
#include "psoc_emmc_pll_regs.h"
#include "psoc_timestamp_regs.h"
#include "cpu_if_regs.h"
#include "cpu_ca53_cfg_regs.h"
#include "cpu_pll_regs.h"
#include "ic_pll_regs.h"
#include "mc_pll_regs.h"
#include "tpc_pll_regs.h"
#include "dma_qm_0_regs.h"
#include "dma_qm_1_regs.h"
#include "dma_qm_2_regs.h"
#include "dma_qm_3_regs.h"
#include "dma_qm_4_regs.h"
#include "dma_ch_0_regs.h"
#include "dma_ch_1_regs.h"
#include "dma_ch_2_regs.h"
#include "dma_ch_3_regs.h"
#include "dma_ch_4_regs.h"
#include "dma_macro_regs.h"
#include "dma_nrtr_regs.h"
#include "pci_nrtr_regs.h"
#include "sram_y0_x0_rtr_regs.h"
#include "sram_y0_x1_rtr_regs.h"
#include "sram_y0_x2_rtr_regs.h"
#include "sram_y0_x3_rtr_regs.h"
#include "sram_y0_x4_rtr_regs.h"
#include "mme_regs.h"
#include "mme_qm_regs.h"
#include "mme_cmdq_regs.h"
#include "mme1_rtr_regs.h"
#include "mme2_rtr_regs.h"
#include "mme3_rtr_regs.h"
#include "mme4_rtr_regs.h"
#include "mme5_rtr_regs.h"
#include "mme6_rtr_regs.h"
#include "tpc0_cfg_regs.h"
#include "tpc1_cfg_regs.h"
#include "tpc2_cfg_regs.h"
#include "tpc3_cfg_regs.h"
#include "tpc4_cfg_regs.h"
#include "tpc5_cfg_regs.h"
#include "tpc6_cfg_regs.h"
#include "tpc7_cfg_regs.h"
#include "tpc0_qm_regs.h"
#include "tpc1_qm_regs.h"
#include "tpc2_qm_regs.h"
#include "tpc3_qm_regs.h"
#include "tpc4_qm_regs.h"
#include "tpc5_qm_regs.h"
#include "tpc6_qm_regs.h"
#include "tpc7_qm_regs.h"
#include "tpc0_cmdq_regs.h"
#include "tpc1_cmdq_regs.h"
#include "tpc2_cmdq_regs.h"
#include "tpc3_cmdq_regs.h"
#include "tpc4_cmdq_regs.h"
#include "tpc5_cmdq_regs.h"
#include "tpc6_cmdq_regs.h"
#include "tpc7_cmdq_regs.h"
#include "tpc0_nrtr_regs.h"
#include "tpc1_rtr_regs.h"
#include "tpc2_rtr_regs.h"
#include "tpc3_rtr_regs.h"
#include "tpc4_rtr_regs.h"
#include "tpc5_rtr_regs.h"
#include "tpc6_rtr_regs.h"
#include "tpc7_nrtr_regs.h"
#include "tpc0_eml_cfg_regs.h"
#include "psoc_etr_regs.h"

#include "psoc_global_conf_masks.h"
#include "dma_macro_masks.h"
#include "dma_qm_0_masks.h"
#include "dma_ch_0_masks.h"
#include "tpc0_qm_masks.h"
#include "tpc0_cmdq_masks.h"
#include "mme_qm_masks.h"
#include "mme_cmdq_masks.h"

Annotation

• Immediate include surface: `goya_blocks.h`, `stlb_regs.h`, `mmu_regs.h`, `pcie_aux_regs.h`, `pcie_wrap_regs.h`, `psoc_global_conf_regs.h`, `psoc_spi_regs.h`, `psoc_mme_pll_regs.h`.
• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.