drivers/accel/habanalabs/include/goya/asic_reg/mc_pll_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/mc_pll_regs.h

Extension

.h

Size

3729 bytes

Lines

105

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_MC_PLL_REGS_H_
#define ASIC_REG_MC_PLL_REGS_H_

/*
 *****************************************
 *   MC_PLL (Prototype: PLL)
 *****************************************
 */

#define mmMC_PLL_NR                                                  0x4A1100

#define mmMC_PLL_NF                                                  0x4A1104

#define mmMC_PLL_OD                                                  0x4A1108

#define mmMC_PLL_NB                                                  0x4A110C

#define mmMC_PLL_CFG                                                 0x4A1110

#define mmMC_PLL_LOSE_MASK                                           0x4A1120

#define mmMC_PLL_LOCK_INTR                                           0x4A1128

#define mmMC_PLL_LOCK_BYPASS                                         0x4A112C

#define mmMC_PLL_DATA_CHNG                                           0x4A1130

#define mmMC_PLL_RST                                                 0x4A1134

#define mmMC_PLL_SLIP_WD_CNTR                                        0x4A1150

#define mmMC_PLL_DIV_FACTOR_0                                        0x4A1200

#define mmMC_PLL_DIV_FACTOR_1                                        0x4A1204

#define mmMC_PLL_DIV_FACTOR_2                                        0x4A1208

#define mmMC_PLL_DIV_FACTOR_3                                        0x4A120C

#define mmMC_PLL_DIV_FACTOR_CMD_0                                    0x4A1220

#define mmMC_PLL_DIV_FACTOR_CMD_1                                    0x4A1224

#define mmMC_PLL_DIV_FACTOR_CMD_2                                    0x4A1228

#define mmMC_PLL_DIV_FACTOR_CMD_3                                    0x4A122C

#define mmMC_PLL_DIV_SEL_0                                           0x4A1280

#define mmMC_PLL_DIV_SEL_1                                           0x4A1284

#define mmMC_PLL_DIV_SEL_2                                           0x4A1288

#define mmMC_PLL_DIV_SEL_3                                           0x4A128C

#define mmMC_PLL_DIV_EN_0                                            0x4A12A0

#define mmMC_PLL_DIV_EN_1                                            0x4A12A4

#define mmMC_PLL_DIV_EN_2                                            0x4A12A8

#define mmMC_PLL_DIV_EN_3                                            0x4A12AC

#define mmMC_PLL_DIV_FACTOR_BUSY_0                                   0x4A12C0

#define mmMC_PLL_DIV_FACTOR_BUSY_1                                   0x4A12C4

#define mmMC_PLL_DIV_FACTOR_BUSY_2                                   0x4A12C8

#define mmMC_PLL_DIV_FACTOR_BUSY_3                                   0x4A12CC

#define mmMC_PLL_CLK_GATER                                           0x4A1300

#define mmMC_PLL_CLK_RLX_0                                           0x4A1310

#define mmMC_PLL_CLK_RLX_1                                           0x4A1314

#define mmMC_PLL_CLK_RLX_2                                           0x4A1318

#define mmMC_PLL_CLK_RLX_3                                           0x4A131C

#define mmMC_PLL_REF_CNTR_PERIOD                                     0x4A1400

#define mmMC_PLL_REF_LOW_THRESHOLD                                   0x4A1410

#define mmMC_PLL_REF_HIGH_THRESHOLD                                  0x4A1420

#define mmMC_PLL_PLL_NOT_STABLE                                      0x4A1430

#define mmMC_PLL_FREQ_CALC_EN                                        0x4A1440

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.