drivers/accel/habanalabs/include/goya/asic_reg/mme_masks.h
Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/goya/asic_reg/mme_masks.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/habanalabs/include/goya/asic_reg/mme_masks.h- Extension
.h- Size
- 85229 bytes
- Lines
- 1537
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef ASIC_REG_MME_MASKS_H_
#define ASIC_REG_MME_MASKS_H_
/*
*****************************************
* MME (Prototype: MME)
*****************************************
*/
/* MME_ARCH_STATUS */
#define MME_ARCH_STATUS_A_SHIFT 0
#define MME_ARCH_STATUS_A_MASK 0x1
#define MME_ARCH_STATUS_B_SHIFT 1
#define MME_ARCH_STATUS_B_MASK 0x2
#define MME_ARCH_STATUS_CIN_SHIFT 2
#define MME_ARCH_STATUS_CIN_MASK 0x4
#define MME_ARCH_STATUS_COUT_SHIFT 3
#define MME_ARCH_STATUS_COUT_MASK 0x8
#define MME_ARCH_STATUS_TE_SHIFT 4
#define MME_ARCH_STATUS_TE_MASK 0x10
#define MME_ARCH_STATUS_LD_SHIFT 5
#define MME_ARCH_STATUS_LD_MASK 0x20
#define MME_ARCH_STATUS_ST_SHIFT 6
#define MME_ARCH_STATUS_ST_MASK 0x40
#define MME_ARCH_STATUS_SB_A_EMPTY_SHIFT 7
#define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
#define MME_ARCH_STATUS_SB_B_EMPTY_SHIFT 8
#define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
#define MME_ARCH_STATUS_SB_CIN_EMPTY_SHIFT 9
#define MME_ARCH_STATUS_SB_CIN_EMPTY_MASK 0x200
#define MME_ARCH_STATUS_SB_COUT_EMPTY_SHIFT 10
#define MME_ARCH_STATUS_SB_COUT_EMPTY_MASK 0x400
#define MME_ARCH_STATUS_SM_IDLE_SHIFT 11
#define MME_ARCH_STATUS_SM_IDLE_MASK 0x800
#define MME_ARCH_STATUS_WBC_AXI_IDLE_SHIFT 12
#define MME_ARCH_STATUS_WBC_AXI_IDLE_MASK 0xF000
#define MME_ARCH_STATUS_SBC_AXI_IDLE_SHIFT 16
#define MME_ARCH_STATUS_SBC_AXI_IDLE_MASK 0x30000
#define MME_ARCH_STATUS_SBB_AXI_IDLE_SHIFT 18
#define MME_ARCH_STATUS_SBB_AXI_IDLE_MASK 0xC0000
#define MME_ARCH_STATUS_SBA_AXI_IDLE_SHIFT 20
#define MME_ARCH_STATUS_SBA_AXI_IDLE_MASK 0x300000
#define MME_ARCH_STATUS_FREE_ACCUMS_SHIFT 22
#define MME_ARCH_STATUS_FREE_ACCUMS_MASK 0x1C00000
/* MME_ARCH_A_BASE_ADDR_HIGH */
#define MME_ARCH_A_BASE_ADDR_HIGH_V_SHIFT 0
#define MME_ARCH_A_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
/* MME_ARCH_B_BASE_ADDR_HIGH */
#define MME_ARCH_B_BASE_ADDR_HIGH_V_SHIFT 0
#define MME_ARCH_B_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
/* MME_ARCH_CIN_BASE_ADDR_HIGH */
#define MME_ARCH_CIN_BASE_ADDR_HIGH_V_SHIFT 0
#define MME_ARCH_CIN_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
/* MME_ARCH_COUT_BASE_ADDR_HIGH */
#define MME_ARCH_COUT_BASE_ADDR_HIGH_V_SHIFT 0
#define MME_ARCH_COUT_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
/* MME_ARCH_BIAS_BASE_ADDR_HIGH */
#define MME_ARCH_BIAS_BASE_ADDR_HIGH_V_SHIFT 0
#define MME_ARCH_BIAS_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
/* MME_ARCH_A_BASE_ADDR_LOW */
#define MME_ARCH_A_BASE_ADDR_LOW_V_SHIFT 0
#define MME_ARCH_A_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
/* MME_ARCH_B_BASE_ADDR_LOW */
#define MME_ARCH_B_BASE_ADDR_LOW_V_SHIFT 0
#define MME_ARCH_B_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
/* MME_ARCH_CIN_BASE_ADDR_LOW */
#define MME_ARCH_CIN_BASE_ADDR_LOW_V_SHIFT 0
#define MME_ARCH_CIN_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
/* MME_ARCH_COUT_BASE_ADDR_LOW */
#define MME_ARCH_COUT_BASE_ADDR_LOW_V_SHIFT 0
#define MME_ARCH_COUT_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
/* MME_ARCH_BIAS_BASE_ADDR_LOW */
#define MME_ARCH_BIAS_BASE_ADDR_LOW_V_SHIFT 0
#define MME_ARCH_BIAS_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
/* MME_ARCH_HEADER */
#define MME_ARCH_HEADER_SIGNAL_MASK_SHIFT 0
#define MME_ARCH_HEADER_SIGNAL_MASK_MASK 0x1F
#define MME_ARCH_HEADER_SIGNAL_EN_SHIFT 5
#define MME_ARCH_HEADER_SIGNAL_EN_MASK 0x20Annotation
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.