drivers/accel/habanalabs/include/goya/asic_reg/mme_qm_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/mme_qm_regs.h

Extension

.h

Size

6575 bytes

Lines

179

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_MME_QM_REGS_H_
#define ASIC_REG_MME_QM_REGS_H_

/*
 *****************************************
 *   MME_QM (Prototype: QMAN)
 *****************************************
 */

#define mmMME_QM_GLBL_CFG0                                           0xD8000

#define mmMME_QM_GLBL_CFG1                                           0xD8004

#define mmMME_QM_GLBL_PROT                                           0xD8008

#define mmMME_QM_GLBL_ERR_CFG                                        0xD800C

#define mmMME_QM_GLBL_ERR_ADDR_LO                                    0xD8010

#define mmMME_QM_GLBL_ERR_ADDR_HI                                    0xD8014

#define mmMME_QM_GLBL_ERR_WDATA                                      0xD8018

#define mmMME_QM_GLBL_SECURE_PROPS                                   0xD801C

#define mmMME_QM_GLBL_NON_SECURE_PROPS                               0xD8020

#define mmMME_QM_GLBL_STS0                                           0xD8024

#define mmMME_QM_GLBL_STS1                                           0xD8028

#define mmMME_QM_PQ_BASE_LO                                          0xD8060

#define mmMME_QM_PQ_BASE_HI                                          0xD8064

#define mmMME_QM_PQ_SIZE                                             0xD8068

#define mmMME_QM_PQ_PI                                               0xD806C

#define mmMME_QM_PQ_CI                                               0xD8070

#define mmMME_QM_PQ_CFG0                                             0xD8074

#define mmMME_QM_PQ_CFG1                                             0xD8078

#define mmMME_QM_PQ_ARUSER                                           0xD807C

#define mmMME_QM_PQ_PUSH0                                            0xD8080

#define mmMME_QM_PQ_PUSH1                                            0xD8084

#define mmMME_QM_PQ_PUSH2                                            0xD8088

#define mmMME_QM_PQ_PUSH3                                            0xD808C

#define mmMME_QM_PQ_STS0                                             0xD8090

#define mmMME_QM_PQ_STS1                                             0xD8094

#define mmMME_QM_PQ_RD_RATE_LIM_EN                                   0xD80A0

#define mmMME_QM_PQ_RD_RATE_LIM_RST_TOKEN                            0xD80A4

#define mmMME_QM_PQ_RD_RATE_LIM_SAT                                  0xD80A8

#define mmMME_QM_PQ_RD_RATE_LIM_TOUT                                 0xD80AC

#define mmMME_QM_CQ_CFG0                                             0xD80B0

#define mmMME_QM_CQ_CFG1                                             0xD80B4

#define mmMME_QM_CQ_ARUSER                                           0xD80B8

#define mmMME_QM_CQ_PTR_LO                                           0xD80C0

#define mmMME_QM_CQ_PTR_HI                                           0xD80C4

#define mmMME_QM_CQ_TSIZE                                            0xD80C8

#define mmMME_QM_CQ_CTL                                              0xD80CC

#define mmMME_QM_CQ_PTR_LO_STS                                       0xD80D4

#define mmMME_QM_CQ_PTR_HI_STS                                       0xD80D8

#define mmMME_QM_CQ_TSIZE_STS                                        0xD80DC

#define mmMME_QM_CQ_CTL_STS                                          0xD80E0

#define mmMME_QM_CQ_STS0                                             0xD80E4

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.