drivers/accel/habanalabs/include/goya/asic_reg/mme5_rtr_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/mme5_rtr_regs.h

Extension

.h

Size

12668 bytes

Lines

331

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_MME5_RTR_REGS_H_
#define ASIC_REG_MME5_RTR_REGS_H_

/*
 *****************************************
 *   MME5_RTR (Prototype: MME_RTR)
 *****************************************
 */

#define mmMME5_RTR_HBW_RD_RQ_E_ARB                                   0x140100

#define mmMME5_RTR_HBW_RD_RQ_W_ARB                                   0x140104

#define mmMME5_RTR_HBW_RD_RQ_N_ARB                                   0x140108

#define mmMME5_RTR_HBW_RD_RQ_S_ARB                                   0x14010C

#define mmMME5_RTR_HBW_RD_RQ_L_ARB                                   0x140110

#define mmMME5_RTR_HBW_E_ARB_MAX                                     0x140120

#define mmMME5_RTR_HBW_W_ARB_MAX                                     0x140124

#define mmMME5_RTR_HBW_N_ARB_MAX                                     0x140128

#define mmMME5_RTR_HBW_S_ARB_MAX                                     0x14012C

#define mmMME5_RTR_HBW_L_ARB_MAX                                     0x140130

#define mmMME5_RTR_HBW_RD_RS_MAX_CREDIT                              0x140140

#define mmMME5_RTR_HBW_WR_RQ_MAX_CREDIT                              0x140144

#define mmMME5_RTR_HBW_RD_RQ_MAX_CREDIT                              0x140148

#define mmMME5_RTR_HBW_RD_RS_E_ARB                                   0x140150

#define mmMME5_RTR_HBW_RD_RS_W_ARB                                   0x140154

#define mmMME5_RTR_HBW_RD_RS_N_ARB                                   0x140158

#define mmMME5_RTR_HBW_RD_RS_S_ARB                                   0x14015C

#define mmMME5_RTR_HBW_RD_RS_L_ARB                                   0x140160

#define mmMME5_RTR_HBW_WR_RQ_E_ARB                                   0x140170

#define mmMME5_RTR_HBW_WR_RQ_W_ARB                                   0x140174

#define mmMME5_RTR_HBW_WR_RQ_N_ARB                                   0x140178

#define mmMME5_RTR_HBW_WR_RQ_S_ARB                                   0x14017C

#define mmMME5_RTR_HBW_WR_RQ_L_ARB                                   0x140180

#define mmMME5_RTR_HBW_WR_RS_E_ARB                                   0x140190

#define mmMME5_RTR_HBW_WR_RS_W_ARB                                   0x140194

#define mmMME5_RTR_HBW_WR_RS_N_ARB                                   0x140198

#define mmMME5_RTR_HBW_WR_RS_S_ARB                                   0x14019C

#define mmMME5_RTR_HBW_WR_RS_L_ARB                                   0x1401A0

#define mmMME5_RTR_LBW_RD_RQ_E_ARB                                   0x140200

#define mmMME5_RTR_LBW_RD_RQ_W_ARB                                   0x140204

#define mmMME5_RTR_LBW_RD_RQ_N_ARB                                   0x140208

#define mmMME5_RTR_LBW_RD_RQ_S_ARB                                   0x14020C

#define mmMME5_RTR_LBW_RD_RQ_L_ARB                                   0x140210

#define mmMME5_RTR_LBW_E_ARB_MAX                                     0x140220

#define mmMME5_RTR_LBW_W_ARB_MAX                                     0x140224

#define mmMME5_RTR_LBW_N_ARB_MAX                                     0x140228

#define mmMME5_RTR_LBW_S_ARB_MAX                                     0x14022C

#define mmMME5_RTR_LBW_L_ARB_MAX                                     0x140230

#define mmMME5_RTR_LBW_SRAM_MAX_CREDIT                               0x140240

#define mmMME5_RTR_LBW_RD_RS_E_ARB                                   0x140250

#define mmMME5_RTR_LBW_RD_RS_W_ARB                                   0x140254

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.