drivers/accel/habanalabs/include/goya/asic_reg/pci_nrtr_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/goya/asic_reg/pci_nrtr_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/goya/asic_reg/pci_nrtr_regs.h
Extension
.h
Size
8254 bytes
Lines
227
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_PCI_NRTR_REGS_H_
#define ASIC_REG_PCI_NRTR_REGS_H_

/*
 *****************************************
 *   PCI_NRTR (Prototype: IF_NRTR)
 *****************************************
 */

#define mmPCI_NRTR_HBW_MAX_CRED                                      0x100

#define mmPCI_NRTR_LBW_MAX_CRED                                      0x120

#define mmPCI_NRTR_DBG_E_ARB                                         0x300

#define mmPCI_NRTR_DBG_W_ARB                                         0x304

#define mmPCI_NRTR_DBG_N_ARB                                         0x308

#define mmPCI_NRTR_DBG_S_ARB                                         0x30C

#define mmPCI_NRTR_DBG_L_ARB                                         0x310

#define mmPCI_NRTR_DBG_E_ARB_MAX                                     0x320

#define mmPCI_NRTR_DBG_W_ARB_MAX                                     0x324

#define mmPCI_NRTR_DBG_N_ARB_MAX                                     0x328

#define mmPCI_NRTR_DBG_S_ARB_MAX                                     0x32C

#define mmPCI_NRTR_DBG_L_ARB_MAX                                     0x330

#define mmPCI_NRTR_SPLIT_COEF_0                                      0x400

#define mmPCI_NRTR_SPLIT_COEF_1                                      0x404

#define mmPCI_NRTR_SPLIT_COEF_2                                      0x408

#define mmPCI_NRTR_SPLIT_COEF_3                                      0x40C

#define mmPCI_NRTR_SPLIT_COEF_4                                      0x410

#define mmPCI_NRTR_SPLIT_COEF_5                                      0x414

#define mmPCI_NRTR_SPLIT_COEF_6                                      0x418

#define mmPCI_NRTR_SPLIT_COEF_7                                      0x41C

#define mmPCI_NRTR_SPLIT_COEF_8                                      0x420

#define mmPCI_NRTR_SPLIT_COEF_9                                      0x424

#define mmPCI_NRTR_SPLIT_CFG                                         0x440

#define mmPCI_NRTR_SPLIT_RD_SAT                                      0x444

#define mmPCI_NRTR_SPLIT_RD_RST_TOKEN                                0x448

#define mmPCI_NRTR_SPLIT_RD_TIMEOUT_0                                0x44C

#define mmPCI_NRTR_SPLIT_RD_TIMEOUT_1                                0x450

#define mmPCI_NRTR_SPLIT_WR_SAT                                      0x454

#define mmPCI_NRTR_WPLIT_WR_TST_TOLEN                                0x458

#define mmPCI_NRTR_SPLIT_WR_TIMEOUT_0                                0x45C

#define mmPCI_NRTR_SPLIT_WR_TIMEOUT_1                                0x460

#define mmPCI_NRTR_HBW_RANGE_HIT                                     0x470

#define mmPCI_NRTR_HBW_RANGE_MASK_L_0                                0x480

#define mmPCI_NRTR_HBW_RANGE_MASK_L_1                                0x484

#define mmPCI_NRTR_HBW_RANGE_MASK_L_2                                0x488

#define mmPCI_NRTR_HBW_RANGE_MASK_L_3                                0x48C

#define mmPCI_NRTR_HBW_RANGE_MASK_L_4                                0x490

#define mmPCI_NRTR_HBW_RANGE_MASK_L_5                                0x494

#define mmPCI_NRTR_HBW_RANGE_MASK_L_6                                0x498

#define mmPCI_NRTR_HBW_RANGE_MASK_L_7                                0x49C

#define mmPCI_NRTR_HBW_RANGE_MASK_H_0                                0x4A0

Annotation

Implementation Notes