drivers/accel/habanalabs/include/goya/asic_reg/pcie_wrap_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/pcie_wrap_regs.h

Extension

.h

Size

11726 bytes

Lines

307

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_PCIE_WRAP_REGS_H_
#define ASIC_REG_PCIE_WRAP_REGS_H_

/*
 *****************************************
 *   PCIE_WRAP (Prototype: PCIE_WRAP)
 *****************************************
 */

#define mmPCIE_WRAP_PHY_RST_N                                        0xC01300

#define mmPCIE_WRAP_OUTSTAND_TRANS                                   0xC01400

#define mmPCIE_WRAP_MASK_REQ                                         0xC01404

#define mmPCIE_WRAP_IND_AWADDR_L                                     0xC01500

#define mmPCIE_WRAP_IND_AWADDR_H                                     0xC01504

#define mmPCIE_WRAP_IND_AWLEN                                        0xC01508

#define mmPCIE_WRAP_IND_AWSIZE                                       0xC0150C

#define mmPCIE_WRAP_IND_AWBURST                                      0xC01510

#define mmPCIE_WRAP_IND_AWLOCK                                       0xC01514

#define mmPCIE_WRAP_IND_AWCACHE                                      0xC01518

#define mmPCIE_WRAP_IND_AWPROT                                       0xC0151C

#define mmPCIE_WRAP_IND_AWVALID                                      0xC01520

#define mmPCIE_WRAP_IND_WDATA_0                                      0xC01524

#define mmPCIE_WRAP_IND_WDATA_1                                      0xC01528

#define mmPCIE_WRAP_IND_WDATA_2                                      0xC0152C

#define mmPCIE_WRAP_IND_WDATA_3                                      0xC01530

#define mmPCIE_WRAP_IND_WSTRB                                        0xC01544

#define mmPCIE_WRAP_IND_WLAST                                        0xC01548

#define mmPCIE_WRAP_IND_WVALID                                       0xC0154C

#define mmPCIE_WRAP_IND_BRESP                                        0xC01550

#define mmPCIE_WRAP_IND_BVALID                                       0xC01554

#define mmPCIE_WRAP_IND_ARADDR_0                                     0xC01558

#define mmPCIE_WRAP_IND_ARADDR_1                                     0xC0155C

#define mmPCIE_WRAP_IND_ARLEN                                        0xC01560

#define mmPCIE_WRAP_IND_ARSIZE                                       0xC01564

#define mmPCIE_WRAP_IND_ARBURST                                      0xC01568

#define mmPCIE_WRAP_IND_ARLOCK                                       0xC0156C

#define mmPCIE_WRAP_IND_ARCACHE                                      0xC01570

#define mmPCIE_WRAP_IND_ARPROT                                       0xC01574

#define mmPCIE_WRAP_IND_ARVALID                                      0xC01578

#define mmPCIE_WRAP_IND_RDATA_0                                      0xC0157C

#define mmPCIE_WRAP_IND_RDATA_1                                      0xC01580

#define mmPCIE_WRAP_IND_RDATA_2                                      0xC01584

#define mmPCIE_WRAP_IND_RDATA_3                                      0xC01588

#define mmPCIE_WRAP_IND_RLAST                                        0xC0159C

#define mmPCIE_WRAP_IND_RRESP                                        0xC015A0

#define mmPCIE_WRAP_IND_RVALID                                       0xC015A4

#define mmPCIE_WRAP_IND_AWMISC_INFO                                  0xC015A8

#define mmPCIE_WRAP_IND_AWMISC_INFO_HDR_34DW_0                       0xC015AC

#define mmPCIE_WRAP_IND_AWMISC_INFO_HDR_34DW_1                       0xC015B0

#define mmPCIE_WRAP_IND_AWMISC_INFO_P_TAG                            0xC015B4

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.