drivers/accel/habanalabs/include/goya/asic_reg/psoc_global_conf_masks.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/psoc_global_conf_masks.h

Extension

.h

Size

26041 bytes

Lines

447

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_
#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_

/*
 *****************************************
 *   PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF)
 *****************************************
 */

/* PSOC_GLOBAL_CONF_NON_RST_FLOPS */
#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT                     0
#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK                      0xFFFFFFFF

/* PSOC_GLOBAL_CONF_PCI_FW_FSM */
#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT                         0
#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK                          0x1

/* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT                 0
#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK                  0x1

/* PSOC_GLOBAL_CONF_BTM_FSM */
#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT                         0
#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK                          0xF

/* PSOC_GLOBAL_CONF_SW_BTM_FSM */
#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT                       0
#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK                        0xF

/* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */
#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT                  0
#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK                   0xF

/* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */
#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT                  0
#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK                   0xFFFFFFFF

/* PSOC_GLOBAL_CONF_SPI_MEM_EN */
#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SHIFT                        0
#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_MASK                         0x1

/* PSOC_GLOBAL_CONF_PRSTN */
#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT                             0
#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK                              0x1

/* PSOC_GLOBAL_CONF_PCIE_EN */
#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT                          0
#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK                           0x1

/* PSOC_GLOBAL_CONF_SPI_IMG_STS */
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_SHIFT                       0
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_MASK                        0x1
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_SHIFT                       1
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_MASK                        0x2
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SHIFT                     2
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_MASK                      0x4
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_SHIFT                       3
#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_MASK                        0x8

/* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT                     0
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK                      0x1
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT                1
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK                 0x2
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT                  2
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK                   0x4
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT                  3
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK                   0x8
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT                4
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK                 0x10
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT                 5
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK                  0x20
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT                      6
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK                       0x40
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT               7
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK                0x80
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT                 8
#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK                  0x100

/* PSOC_GLOBAL_CONF_SCRATCHPAD */
#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT                        0
#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK                         0xFFFFFFFF

/* PSOC_GLOBAL_CONF_SEMAPHORE */
#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT                         0
#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK                          0xFFFFFFFF

/* PSOC_GLOBAL_CONF_WARM_REBOOT */
#define PSOC_GLOBAL_CONF_WARM_REBOOT_CNTR_SHIFT                      0
#define PSOC_GLOBAL_CONF_WARM_REBOOT_CNTR_MASK                       0xFFFFFFFF

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.