drivers/accel/habanalabs/include/goya/asic_reg/psoc_mme_pll_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/psoc_mme_pll_regs.h

Extension

.h

Size

3753 bytes

Lines

105

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_PSOC_MME_PLL_REGS_H_
#define ASIC_REG_PSOC_MME_PLL_REGS_H_

/*
 *****************************************
 *   PSOC_MME_PLL (Prototype: PLL)
 *****************************************
 */

#define mmPSOC_MME_PLL_NR                                            0xC71100

#define mmPSOC_MME_PLL_NF                                            0xC71104

#define mmPSOC_MME_PLL_OD                                            0xC71108

#define mmPSOC_MME_PLL_NB                                            0xC7110C

#define mmPSOC_MME_PLL_CFG                                           0xC71110

#define mmPSOC_MME_PLL_LOSE_MASK                                     0xC71120

#define mmPSOC_MME_PLL_LOCK_INTR                                     0xC71128

#define mmPSOC_MME_PLL_LOCK_BYPASS                                   0xC7112C

#define mmPSOC_MME_PLL_DATA_CHNG                                     0xC71130

#define mmPSOC_MME_PLL_RST                                           0xC71134

#define mmPSOC_MME_PLL_SLIP_WD_CNTR                                  0xC71150

#define mmPSOC_MME_PLL_DIV_FACTOR_0                                  0xC71200

#define mmPSOC_MME_PLL_DIV_FACTOR_1                                  0xC71204

#define mmPSOC_MME_PLL_DIV_FACTOR_2                                  0xC71208

#define mmPSOC_MME_PLL_DIV_FACTOR_3                                  0xC7120C

#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_0                              0xC71220

#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_1                              0xC71224

#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_2                              0xC71228

#define mmPSOC_MME_PLL_DIV_FACTOR_CMD_3                              0xC7122C

#define mmPSOC_MME_PLL_DIV_SEL_0                                     0xC71280

#define mmPSOC_MME_PLL_DIV_SEL_1                                     0xC71284

#define mmPSOC_MME_PLL_DIV_SEL_2                                     0xC71288

#define mmPSOC_MME_PLL_DIV_SEL_3                                     0xC7128C

#define mmPSOC_MME_PLL_DIV_EN_0                                      0xC712A0

#define mmPSOC_MME_PLL_DIV_EN_1                                      0xC712A4

#define mmPSOC_MME_PLL_DIV_EN_2                                      0xC712A8

#define mmPSOC_MME_PLL_DIV_EN_3                                      0xC712AC

#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_0                             0xC712C0

#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_1                             0xC712C4

#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_2                             0xC712C8

#define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_3                             0xC712CC

#define mmPSOC_MME_PLL_CLK_GATER                                     0xC71300

#define mmPSOC_MME_PLL_CLK_RLX_0                                     0xC71310

#define mmPSOC_MME_PLL_CLK_RLX_1                                     0xC71314

#define mmPSOC_MME_PLL_CLK_RLX_2                                     0xC71318

#define mmPSOC_MME_PLL_CLK_RLX_3                                     0xC7131C

#define mmPSOC_MME_PLL_REF_CNTR_PERIOD                               0xC71400

#define mmPSOC_MME_PLL_REF_LOW_THRESHOLD                             0xC71410

#define mmPSOC_MME_PLL_REF_HIGH_THRESHOLD                            0xC71420

#define mmPSOC_MME_PLL_PLL_NOT_STABLE                                0xC71430

#define mmPSOC_MME_PLL_FREQ_CALC_EN                                  0xC71440

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.