drivers/accel/habanalabs/include/goya/asic_reg/psoc_pci_pll_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/psoc_pci_pll_regs.h

Extension

.h

Size

3753 bytes

Lines

105

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_PSOC_PCI_PLL_REGS_H_
#define ASIC_REG_PSOC_PCI_PLL_REGS_H_

/*
 *****************************************
 *   PSOC_PCI_PLL (Prototype: PLL)
 *****************************************
 */

#define mmPSOC_PCI_PLL_NR                                            0xC72100

#define mmPSOC_PCI_PLL_NF                                            0xC72104

#define mmPSOC_PCI_PLL_OD                                            0xC72108

#define mmPSOC_PCI_PLL_NB                                            0xC7210C

#define mmPSOC_PCI_PLL_CFG                                           0xC72110

#define mmPSOC_PCI_PLL_LOSE_MASK                                     0xC72120

#define mmPSOC_PCI_PLL_LOCK_INTR                                     0xC72128

#define mmPSOC_PCI_PLL_LOCK_BYPASS                                   0xC7212C

#define mmPSOC_PCI_PLL_DATA_CHNG                                     0xC72130

#define mmPSOC_PCI_PLL_RST                                           0xC72134

#define mmPSOC_PCI_PLL_SLIP_WD_CNTR                                  0xC72150

#define mmPSOC_PCI_PLL_DIV_FACTOR_0                                  0xC72200

#define mmPSOC_PCI_PLL_DIV_FACTOR_1                                  0xC72204

#define mmPSOC_PCI_PLL_DIV_FACTOR_2                                  0xC72208

#define mmPSOC_PCI_PLL_DIV_FACTOR_3                                  0xC7220C

#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_0                              0xC72220

#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_1                              0xC72224

#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_2                              0xC72228

#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_3                              0xC7222C

#define mmPSOC_PCI_PLL_DIV_SEL_0                                     0xC72280

#define mmPSOC_PCI_PLL_DIV_SEL_1                                     0xC72284

#define mmPSOC_PCI_PLL_DIV_SEL_2                                     0xC72288

#define mmPSOC_PCI_PLL_DIV_SEL_3                                     0xC7228C

#define mmPSOC_PCI_PLL_DIV_EN_0                                      0xC722A0

#define mmPSOC_PCI_PLL_DIV_EN_1                                      0xC722A4

#define mmPSOC_PCI_PLL_DIV_EN_2                                      0xC722A8

#define mmPSOC_PCI_PLL_DIV_EN_3                                      0xC722AC

#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_0                             0xC722C0

#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_1                             0xC722C4

#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_2                             0xC722C8

#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_3                             0xC722CC

#define mmPSOC_PCI_PLL_CLK_GATER                                     0xC72300

#define mmPSOC_PCI_PLL_CLK_RLX_0                                     0xC72310

#define mmPSOC_PCI_PLL_CLK_RLX_1                                     0xC72314

#define mmPSOC_PCI_PLL_CLK_RLX_2                                     0xC72318

#define mmPSOC_PCI_PLL_CLK_RLX_3                                     0xC7231C

#define mmPSOC_PCI_PLL_REF_CNTR_PERIOD                               0xC72400

#define mmPSOC_PCI_PLL_REF_LOW_THRESHOLD                             0xC72410

#define mmPSOC_PCI_PLL_REF_HIGH_THRESHOLD                            0xC72420

#define mmPSOC_PCI_PLL_PLL_NOT_STABLE                                0xC72430

#define mmPSOC_PCI_PLL_FREQ_CALC_EN                                  0xC72440

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.