drivers/accel/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_masks.h
Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_masks.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_masks.h- Extension
.h- Size
- 17981 bytes
- Lines
- 347
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef ASIC_REG_TPC0_EML_CFG_MASKS_H_
#define ASIC_REG_TPC0_EML_CFG_MASKS_H_
/*
*****************************************
* TPC0_EML_CFG (Prototype: TPC_EML_CFG)
*****************************************
*/
/* TPC0_EML_CFG_DBG_CNT */
#define TPC0_EML_CFG_DBG_CNT_DBG_ENTER_SHIFT 0
#define TPC0_EML_CFG_DBG_CNT_DBG_ENTER_MASK 0x1
#define TPC0_EML_CFG_DBG_CNT_DBG_EN_SHIFT 1
#define TPC0_EML_CFG_DBG_CNT_DBG_EN_MASK 0x2
#define TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT 2
#define TPC0_EML_CFG_DBG_CNT_CORE_RST_MASK 0x4
#define TPC0_EML_CFG_DBG_CNT_DCACHE_INV_SHIFT 4
#define TPC0_EML_CFG_DBG_CNT_DCACHE_INV_MASK 0x10
#define TPC0_EML_CFG_DBG_CNT_ICACHE_INV_SHIFT 5
#define TPC0_EML_CFG_DBG_CNT_ICACHE_INV_MASK 0x20
#define TPC0_EML_CFG_DBG_CNT_DBG_EXIT_SHIFT 6
#define TPC0_EML_CFG_DBG_CNT_DBG_EXIT_MASK 0x40
#define TPC0_EML_CFG_DBG_CNT_SNG_STEP_SHIFT 7
#define TPC0_EML_CFG_DBG_CNT_SNG_STEP_MASK 0x80
#define TPC0_EML_CFG_DBG_CNT_BP_DBGSW_EN_SHIFT 16
#define TPC0_EML_CFG_DBG_CNT_BP_DBGSW_EN_MASK 0x10000
/* TPC0_EML_CFG_DBG_STS */
#define TPC0_EML_CFG_DBG_STS_DBG_MODE_SHIFT 0
#define TPC0_EML_CFG_DBG_STS_DBG_MODE_MASK 0x1
#define TPC0_EML_CFG_DBG_STS_CORE_READY_SHIFT 1
#define TPC0_EML_CFG_DBG_STS_CORE_READY_MASK 0x2
#define TPC0_EML_CFG_DBG_STS_DURING_KERNEL_SHIFT 2
#define TPC0_EML_CFG_DBG_STS_DURING_KERNEL_MASK 0x4
#define TPC0_EML_CFG_DBG_STS_ICACHE_IDLE_SHIFT 3
#define TPC0_EML_CFG_DBG_STS_ICACHE_IDLE_MASK 0x8
#define TPC0_EML_CFG_DBG_STS_DCACHE_IDLE_SHIFT 4
#define TPC0_EML_CFG_DBG_STS_DCACHE_IDLE_MASK 0x10
#define TPC0_EML_CFG_DBG_STS_QM_IDLE_SHIFT 5
#define TPC0_EML_CFG_DBG_STS_QM_IDLE_MASK 0x20
#define TPC0_EML_CFG_DBG_STS_WQ_IDLE_SHIFT 6
#define TPC0_EML_CFG_DBG_STS_WQ_IDLE_MASK 0x40
#define TPC0_EML_CFG_DBG_STS_MSS_IDLE_SHIFT 7
#define TPC0_EML_CFG_DBG_STS_MSS_IDLE_MASK 0x80
#define TPC0_EML_CFG_DBG_STS_DBG_CAUSE_SHIFT 8
#define TPC0_EML_CFG_DBG_STS_DBG_CAUSE_MASK 0xFFFFFF00
/* TPC0_EML_CFG_DBG_PADD */
#define TPC0_EML_CFG_DBG_PADD_ADDRESS_SHIFT 0
#define TPC0_EML_CFG_DBG_PADD_ADDRESS_MASK 0xFFFFFFFF
/* TPC0_EML_CFG_DBG_PADD_COUNT */
#define TPC0_EML_CFG_DBG_PADD_COUNT_COUNT_SHIFT 0
#define TPC0_EML_CFG_DBG_PADD_COUNT_COUNT_MASK 0xFF
/* TPC0_EML_CFG_DBG_PADD_COUNT_MATCH */
#define TPC0_EML_CFG_DBG_PADD_COUNT_MATCH_COUNT_SHIFT 0
#define TPC0_EML_CFG_DBG_PADD_COUNT_MATCH_COUNT_MASK 0xFF
/* TPC0_EML_CFG_DBG_PADD_EN */
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE0_SHIFT 0
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE0_MASK 0x1
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE1_SHIFT 1
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE1_MASK 0x2
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE2_SHIFT 2
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE2_MASK 0x4
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE3_SHIFT 3
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE3_MASK 0x8
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE4_SHIFT 4
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE4_MASK 0x10
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE5_SHIFT 5
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE5_MASK 0x20
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE6_SHIFT 6
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE6_MASK 0x40
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE7_SHIFT 7
#define TPC0_EML_CFG_DBG_PADD_EN_ENABLE7_MASK 0x80
/* TPC0_EML_CFG_DBG_VPADD_HIGH */
#define TPC0_EML_CFG_DBG_VPADD_HIGH_ADDRESS_SHIFT 0
#define TPC0_EML_CFG_DBG_VPADD_HIGH_ADDRESS_MASK 0x1FF
/* TPC0_EML_CFG_DBG_VPADD_LOW */
#define TPC0_EML_CFG_DBG_VPADD_LOW_ADDRESS_SHIFT 0
#define TPC0_EML_CFG_DBG_VPADD_LOW_ADDRESS_MASK 0x1FF
/* TPC0_EML_CFG_DBG_VPADD_COUNT */
#define TPC0_EML_CFG_DBG_VPADD_COUNT_COUNT_SHIFT 0
#define TPC0_EML_CFG_DBG_VPADD_COUNT_COUNT_MASK 0xFF
/* TPC0_EML_CFG_DBG_VPADD_COUNT_MATCH */Annotation
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.