drivers/accel/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/goya/asic_reg/tpc0_eml_cfg_regs.h

Extension

.h

Size

12122 bytes

Lines

313

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_TPC0_EML_CFG_REGS_H_
#define ASIC_REG_TPC0_EML_CFG_REGS_H_

/*
 *****************************************
 *   TPC0_EML_CFG (Prototype: TPC_EML_CFG)
 *****************************************
 */

#define mmTPC0_EML_CFG_DBG_CNT                                       0x3040000

#define mmTPC0_EML_CFG_DBG_STS                                       0x3040004

#define mmTPC0_EML_CFG_DBG_PADD_0                                    0x3040008

#define mmTPC0_EML_CFG_DBG_PADD_1                                    0x304000C

#define mmTPC0_EML_CFG_DBG_PADD_2                                    0x3040010

#define mmTPC0_EML_CFG_DBG_PADD_3                                    0x3040014

#define mmTPC0_EML_CFG_DBG_PADD_4                                    0x3040018

#define mmTPC0_EML_CFG_DBG_PADD_5                                    0x304001C

#define mmTPC0_EML_CFG_DBG_PADD_6                                    0x3040020

#define mmTPC0_EML_CFG_DBG_PADD_7                                    0x3040024

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_0                              0x3040028

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_1                              0x304002C

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_2                              0x3040030

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_3                              0x3040034

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_4                              0x3040038

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_5                              0x304003C

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_6                              0x3040040

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_7                              0x3040044

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_0                        0x3040048

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_1                        0x304004C

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_2                        0x3040050

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_3                        0x3040054

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_4                        0x3040058

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_5                        0x304005C

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_6                        0x3040060

#define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_7                        0x3040064

#define mmTPC0_EML_CFG_DBG_PADD_EN                                   0x3040068

#define mmTPC0_EML_CFG_DBG_VPADD_HIGH_0                              0x304006C

#define mmTPC0_EML_CFG_DBG_VPADD_HIGH_1                              0x3040070

#define mmTPC0_EML_CFG_DBG_VPADD_LOW_0                               0x3040074

#define mmTPC0_EML_CFG_DBG_VPADD_LOW_1                               0x3040078

#define mmTPC0_EML_CFG_DBG_VPADD_COUNT_0                             0x304007C

#define mmTPC0_EML_CFG_DBG_VPADD_COUNT_1                             0x3040080

#define mmTPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_0                       0x3040084

#define mmTPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_1                       0x3040088

#define mmTPC0_EML_CFG_DBG_VPADD_EN                                  0x304008C

#define mmTPC0_EML_CFG_DBG_SPADD_HIGH_0                              0x3040090

#define mmTPC0_EML_CFG_DBG_SPADD_HIGH_1                              0x3040094

#define mmTPC0_EML_CFG_DBG_SPADD_LOW_0                               0x3040098

#define mmTPC0_EML_CFG_DBG_SPADD_LOW_1                               0x304009C

#define mmTPC0_EML_CFG_DBG_SPADD_COUNT_0                             0x30400A0

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.